1. Hardware Implementation of Simplex Algorithm for Flash ADC Optimization
Yuta Toriyama
April 09, 2010

2. Outline Probabilistic Flash ADC Problem
Representing the Flash ADC as a network graph
Linear Program & Simplex Algorithm
Hardware Implementation
Conclusion

3. Project Goal
Goal: Hardware Implementation Simplex Algorithm for use with Flash ADC optimization
Accompanies design of ADC for low-power bio-medical applications which could allow for non-uniform quantization
Need small devices and/or lower supply voltages
Problem: The relative process variability increases
IC design today is largely application driven. The applications enforce constraints which thereby influence our design methodologies. Example applications....

4. Flash ADC Yield
Yield: % that measures the proportion of ADCs with correct functionality. Decision levels from V0 to VN are monotonically increasing. 1 1 1 1

5. Flash ADC Yield Assume a Gaussian pdf: & Solid line – calculated yield
X – 10,000 pt. Monte Carlo

6. Probabilistic Approach
Problem:
Choose the active comparators
Turn off power to non- working comparators
Constraints:
Maximize SNR
Requirements:
Threshold values and indexes of chosen comparators must be monotonically increasing
Single 1 output to decoder 1 X 1 1 X
Logic
Encoder X X

7. Network Formulation of ADC1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

8. Cost Vector Formulation
Calculate the noise power contribution of each arc: Vj
Ck =
for all k = {1,2,Numarcs} Vi
di = 4
Allows for the inclusion of non-uniform distributions

9. LP Formulation maximize cTx s.t. Ax = [1 0 0 . . .-1]T 0 ≤ xi ≤ 1, i
Optimal solution satisfies xi  {0,1}
Arcs with xi=1 identify the path from V1 to VN that maximizes the SNR for a given input pdf 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

10. Simplex Algorithm
Simplex algorithm solves the LP very quickly even for large matrices
Main operation is series of Gaussian eliminations
Things to note:
initial matrix setup
finding an initial basic feasible solution 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

11. Simplex Algorithm
Simplex algorithm solves the LP very quickly even for large matrices
Main operation is series of Gaussian eliminations
Things to note:
initial matrix setup
finding an initial basic feasible solution 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

12. Simplex Algorithm
Simplex algorithm solves the LP very quickly even for large matrices
Main operation is series of Gaussian eliminations
Things to note:
initial matrix setup
finding an initial basic feasible solution 1 2 3 4 5 6 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 1 -1 1 -1 1 -1 1 -1 1 -1
= A
nodes
arcs

13. Hardware Implementation
Realized on IBOB (?)
Xilinx Virtex-II Pro 2VP50 FPGA
Simulink Xilinx Blockset
Given:
Decision thresholds of each comparator
(Cutoff threshold of arc cost)
Needs to:
Create the A matrix
Create the cost vector
Run the Simplex Algorithm
Main Issue: Resource Usage

14. Resource Usage
Creating the cost vector requires many additions and multiplications
Complexity
The matrix we want is huge:
N=210 comparators = number of rows
Cost cutoff to limit number of columns

15. Storing the Big Matrix
MATLAB simulations of step-by-step simplex algorithm to observe characteristics of matrix
Special Characteristics we need to exploit
Sparse
Only non-zero elements are +1 / -1
Don’t need the xi ≤ 1 constraint
maximize cTx
Try to balance implementation feasibility and resource usage
s.t. Ax = [ ]T
0 ≤ xi ≤ 1, i
Store in a compressed format
(x, y, sign)

16. Work in Progress
Creation of the A matrix and cost vector have been implemented and put on FPGA
To be done:
Simplex Algorithm
Optimizations (?)
Wordlength
Timing
The Simplex Algorithm is a series of Gaussian eliminations
Need to come up with hardware design, given the way the matrix is stored in memory

17. Conclusions
By modeling the system as a network graph, the maximum SNR can be determined using the Simplex method
Hardware implementation seems feasible, though ASIC realization is probably impractical

18. References
Bayliss, S.; Bouganis, C.; Constantinides, G. A.; Luk, W.; , "An FPGA implementation of the simplex algorithm," Field Programmable Technology, FPT IEEE International Conference on , vol., no., pp.49-56, Dec
Schutz, B.; Klindworth, A.; , "A VLSI-chip for a hardware-accelerator for the simplex-method," ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International , vol., no., pp , Sep 1992.
Stathis, P.; Cheresiz, D.; Vassiliadis, S.; Juurlink, B.; , "Sparse matrix transpose unit," Parallel and Distributed Processing Symposium, Proceedings. 18th International , vol., no., pp. 90, April 2004.
Prasanna, V.K.; Morris, G.R.; , "Sparse Matrix Computations on Reconfigurable Hardware," Computer , vol.40, no.3, pp.58-64, March 2007.