1. ECE 352 Digital System Fundamentals
FSM Design and Verification
In this video, we will work through some examples of finite state machine design and verification.

2. State Diagram Formulation
Design a state diagram that implements the following specification:
Output a 1 whenever the circuit recognizes a sequence of “110” within a serial bit pattern
Serial input: information arrives one bit at a time
Each active clock edge marks a new bit
Serial sequences are generally specified from oldest to newest
Design Process
Is the description sufficient? Do we need more information?
Does this description indicate Mealy or Moore?
Determine states required, using placeholders for state values, and reusing states whenever possible.
In these examples, we are given a specification that our circuit must accept a serial data stream as an input, and recognize when the pattern 110 is present in that serial data. A serial input is a single circuit input that provides information one bit at a time, at successive clock edges. The sequence 110 refers to the case where the input is 1 at a clock edge, 1 again at the following clock edge, and then 0 at the clock edge after that. When our circuit sees this pattern, it is to output a 1. It is to output a 0 at all other times.
At first glance, the description seems fairly complete. But we actually need more information. One problem is that the description does not indicate, either implicitly or explicitly, if this should be a Mealy or Moore machine. If the output must be based on the 3 previous input values, it is a Moore machine. If it must be based on the 2 previous input values and the current input value, it is a Mealy machine. Normally, we would need to clarify which design type is needed.
However, for this example, we’ll design both Mealy and Moore versions, starting with the state diagram for the Moore machine.

3. Version 1: Moore Machine
Need to start somewhere…
Start with Reset state!
Haven’t seen a useful part of the pattern yet…
State “Nada” (“Nothing”)
A=0 doesn’t start a pattern
A=1 starts a pattern
State “1”
A=0 ruins pattern: start over
A=1 continues the pattern
State “11”
A=0 completes the pattern
A=1 neither continues nor ruins pattern (still have “11”)
State “110”
A=0: start over…
A=1: start over with first 1
So, where do we start? Well, usually the best place to start is at the beginning. When the machine begins operation in its reset state, there is no “past”, so there are no past input values. We’ll call the reset state “Nada” to indicate that when in this state, we have not yet seen the start of a pattern. It is good practice to use meaningful state names while creating the state diagram so that you know the significance of a state just by looking at it. Since it is a Moore implementation, the output depends only on the current state. We have not seen the pattern if we’re in this state, so its output is 0.
In state Nada, two things can happen. If the input A is a 0, we still have not seen a 1 to start the pattern, so we remain in that state. If the input A is a 1, we have now seen the start of a pattern, so we need to create a new state to keep track of this. Since the state indicates we’ve seen a single 1, we name it “1”.
Now we look at what happens for the two possible input values when state 1 is the current state. If the input is a 0, we no longer have the start of a pattern, so we go back to state Nada. If the input is a 1, we have seen another part of our pattern, so we create a new state that signifies having seen two 1’s in a row, and name it appropriately.
In state 11, an input of 0 completes the pattern, so we need to go to a new state signifying that. We give the 110 state an output of 1 to indicate that if that is the current state, we have detected the pattern. Back in state 11, we still need to react to an input value of 1. In that case, we have not completed our pattern, but we still have two 1s in a row, so we stay in that state.
Finally, in state 110, if the input is 0, the recent inputs no longer form our pattern, so we start over in state Nada. However, if the input is a 1, we may have the beginning of a new pattern, so we go back to state 1. That completes the state diagram for the Moore implementation.

4. Version 2: Mealy Machine
Start with the reset…
State “Nada”
A=0 doesn’t start a pattern
A=1 starts a pattern
State “1”
A=0 ruins pattern: start over
A=1 continues pattern
State “11”
A=0 completes pattern; start over for next
A=1 holds place in pattern
Mealy needs fewer states than Moore for similar functionality
Remember, the functionality is not the same
In the Mealy implementation, we again start with the reset state. In the Nada state we have the same behavior as the Moore machine, but remember that in the Mealy machine the output value must be noted on the state transitions, not in the state.
The rationale for state 1 is the same as it was for the Moore machine, and we again create a state 11 that signifies that the two previous input values were 11.
In state 11, though, the difference between Mealy and Moore becomes apparent. If the current input value is 0, the pattern is complete, and the output must be 1. This transition goes back to Nada since the 0 input value does not help build a new pattern, and we need to start over from the beginning. However, if the current input is a 1, we still have two 1s towards our pattern, so we stay in state 11. But since the pattern isn’t complete, the output is 0.
Note that the Mealy machine needs fewer states, and detects the pattern earlier, than the Moore machine. This will generally be the case because a Mealy machine reacts to the current input value, not just the past ones. It is important to realize that the behavior of these two implementations, although similar, is not identical.

5. State Assignment Given a state diagram, assign state numbers
If m states, must be at least n flip-flops, where 2n≥m
Sometimes use more than necessary…
“Minimum FF” design uses as few FFs as possible
Choice of state numbers can affect the complexity of the next-state and output logic!
Determine the reset state
Usually is the first state we created
Often is assigned the value 0 for reset
But not always!
Once we have a state diagram, we need to determine the number of required flip-flops and assign numbers to the states.
A minimum FF state assignment, as you might guess, uses as few flip-flops as possible. Later in this course you will see a different methodology that intentionally uses more flip-flops than the minimum to simplify the design process.
Remember that the choice of state values will affect the complexity of the combinational logic required to implement our design. We also need to correctly implement the reset behavior so that circuit’s master reset puts it into the correct initial state. The initial state is often assigned state number 0, but it can be any value.

6. Example Used meaningful names to help us build diagram
Now need to pick binary state encoding
Doesn’t have to be Gray code, but it works well here
State names were very useful when designing the state diagram itself, but now we need to assign state numbers. One technique for assigning state numbers is to use a Gray code along state trajectories. We will use this technique in these examples. Note that the Mealy machine has one unused state.
Mealy has unused state 10

7. State Machine Design with D FFs
Draw state diagram based on specification
Derive state table from state diagram
Truth table for the next state logic and output logic
Optimize next state and output logic
Solve for each flip-flop input and each output
Use K-maps to optimize
Draw schematic diagram
Verify through simulation that circuit operation is correct (functional and timing-based)
Now we need to complete a state table for each of our designs. The state table is a tabular representation of the state diagram, so creating it is really just transcription. Then we use the state table to design the combinational logic that will drive each flip-flop input and the circuit output. Once we’ve implemented the circuit, we’ll also need to test it to verify that it works.

8. Example: Moore Machine
The Moore machine has 4 states, so we need two flip-flops. Once we complete the state table, we use that information to complete K-maps for D1, D0 and output Y. In terms of these signals, the state table is just like a truth table. Pause here for a moment and make sure that you understand how the state table was created from the state diagram, and then how it was used to create the K-maps and logic equations.
D1 = Q1Q0 + Q0A
D0 = A
Y = Q1  Q0

9. Example: Mealy Machine
The Mealy machine also requires two flip-flops, but it only uses 3 states. In this case, state 10 is unused. Let’s assume that if we ever get in that state through some transient error, we don’t care what happens. We can then use the don’t-cares to our advantage in the K-maps. Pause here for a moment to review the state table, K-maps, and logic equations.
D1 = Q0 A
D0 = A
Y = Q1  A

10. Example Circuits Moore Mealy D1 = Q1Q0 + Q0A D1 = Q0 A D0 = A D0 = A
can factor out Q0
D0 = A
D0 = A
Y = Q1  Q0
Y = Q1  A
Here we’ve implemented the logic equations for each circuit. In this case, the Mealy machine is simpler, as we’d expect since we used the don’t-care conditions to optimize the circuit.

11. Verification Show that the circuit matches the original specification
Exhaustive testing is only practical for smaller circuits, and cannot test all possible sequences
Instead test each transition and output, with a minimum set of input vectors (minimum  check correctness with less effort)
Get to each state using reset and/or a sequence of inputs
Leave each state using all possible input combinations (2#inputs)
Verify against both specification and state diagram
Don’t just verify against equations in case they are incorrect
Output the current state while testing
You need to know what state it is actually in!
After creating the circuit, we need to test it. With sequential circuits, it’s impossible to test for all sequences of all input values. Instead, we test each state transition to ensure the circuit behaves as expected. That means we need to design a test sequence that checks every possible input value in every possible state.
When you do this testing, be sure that you check the machine’s operation against both the state diagram and the specification.
You can’t know that a state machine made the correct transition unless you can observe its state, so always add extra output pins for the state when testing. Having the next state visible can be helpful as well, although you can always look at what happens at the next clock edge.

12. Example Verification
Create input sequence to test Mealy version of pattern recognizer
Remember: do not change input values at the same time as the active clock edge!
test vector:
reset 1 1 1 1 1
Now let’s verify the Mealy version of our pattern recognizer. We determine a test sequence to exercise every state transition of the circuit. First we use the reset to put the circuit in state 0, and then we methodically work our way through each state transition, trying to minimize the length of the test. We only repeat a transition if we need to in order to test other transitions later in the diagram. In this case, we can test all 6 state transitions using only 7 clock periods.
When you create the test waveform, be sure not to change input values at the same time as the active clock edge, or the simulator won’t know what to do (and neither would a real flip-flop). An easy way to avoid problems is to only change the inputs at the inactive edge of the clock.

13. Example Verification How does this look on a waveform?
(positive-edge triggered)
Showing current state & next state each as 2-bit vector
Next we can run a simulation and verify that the circuit’s behavior is correct. We’ll use positive-edge triggered flip-flops, so we’ll change our input on the negative clock edge. Note that we displayed the current and next state as 2-bit values. This grouping can make it easier to interpret the simulation output, and is a common feature on simulation tools. The resulting waveform shows that our state machine correctly detects the pattern when it occurs in the test sequence.

14. ECE 352 Digital System Fundamentals
FSM Design and Verification
That concludes this video. A methodical approach to the design and verification of state machines is essential for creating correct and efficient state machine circuits.