1. Analysis of a Packet Switch with Memories Running Slower than the Line Rate
Write about the funding
Sundar Iyer, Amr Awadallah, Nick McKeown
Departments of Electrical Engineering & Computer Science, Stanford University

2. Problem Statement Motivation:
To design an extremely high speed packet switch.
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3. A Multi-Terabit OQ Switch
Line Rate
OC3072
4XOC768
160Gb/s
1cell/2ns
Line Rate
OC3072
4XOC768
160Gb/s
1cell/2ns 1 1 2 2
Output Queued Switch 63 63 64 64
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4. Main Problem How to buffer cells in a memory at a rate of 1ns ?
Conventional SRAM
Buffer
Memory
Write Rate R
1 cell in 2 ns
Read Rate R
1 cell in 2 ns 3 2 2 1 1
How to buffer cells in a memory at a rate of 1ns ?
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5. Problem Statement Redefined
Motivation: To design an extremely high speed packet switch with memories running slower than the line rate.
This talk:
Is about the analysis of an obvious approach.
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6. Architecture of a PPS Definition:
A PPS is comprised of multiple identical lower-speed packet-switches operating independently and in parallel. An incoming stream of packets is spread, packet-by-packet, by a demultiplexor across the slower packet-switches, then recombined by a multiplexor at the output.
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7. Architecture of a PPS Demultiplexor OQ Switch Multiplexor (R/k) (R/k)1 2 3
N=4 1 1
Demultiplexor
Multiplexor R
OQ Switch R 2
Demultiplexor 2
Multiplexor R R 3
OQ Switch
Demultiplexor
Multiplexor R R
k=3
N=4
(R/k)
(R/k)
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8. Parallel Packet Switch Questions
Can it behave like a single big output queued switch?
Can it provide delay guarantees, strict-priorities, WFQ, …?
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9. Precise Emulation of an OQ Switch
Yes No =? R
PPS
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10. Emulation Scenario
Layer 1 R 4 1 2 3 5 1 4 2 3 1 4 5 1 2 3 R 1 2 3
N=4 1 2 1 4 2 1 3 5 1 2 3 4 3 2 1 1 2 3 4 5 4 1 2 3
R/3 R R
Layer 2 2 2 1 2 3 4 5 R R 3
R/3
Layer 3 R R
N=4
R/3
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11. Why is there no Choice at the Input ?
Layer 1 5 j 4 1 2 3 1 2 3 j 4 5 j 4 1 2 3 j 4 1 2 3 R R 1 3
N=4 1 1 2 3 4 R R
Layer 2 2 2 R R 3
Layer 3 R R
N=4
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12. Result of no Choice 4 1 2 3 5 4 5 j j 1 2 3 4 Layer 1 R R 1 1 R R
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13. How does one Increase Choice ? Speedup
Layer 1 j 1 j 1 5 1 4 j 2 3 j 5 4 1 2 3 5 j 1 4 2 3 R R 1
(2R/3)
(2R/3) 1 3
N=4 1 R R
Layer 2 2 2 R R 3
Layer 3 R R
N=4
(2R/3)
(2R/3)
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14. Effect of Speedup on Choice
Layer 1
2R/k
Layer 2 R
A speedup of S= 2,
with k= 10 links
Layer 9
Layer 10
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15. Available Input Link Set (AIL)
Definition
Available Input Link Set (AIL)
AIL(i,n) is the set of layers to which external input port i can start writing a cell to, at time slot n.
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16. Departure Time of a Cell (n’)
Definition
Departure Time of a Cell (n’)
The departure time of a cell, n’, is the time it would have departed from an equivalent FIFO OQ switch.
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17. Available Output Link Set (AOL)
Definition
Available Output Link Set (AOL)
AOL(j,n’) is the set of layers that output j can start reading a cell from, at time slot n’.
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18. Main Observation Inputs can only send to the AIL set.
Outputs can only read from the AOL set.
Layer 1 R R 4 1 1
(2R/3)
(2R/3) 1 3
N=4 5 1 j 1 j R R
Layer 2 2 2 2 2 2 2 R R 3
Layer 3 3 R R
N=4
(2R/3)
(2R/3)
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19. Lower Bounds on Choice Sets
Minimum size of AIL, AOL:
|AIL|, >= Total – Maximum number of |AOL| links links which can have cells in progress
= k ( k/S )
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20. Assurance of Choice
A cell must be sent to a link which belongs to both the AIL and the AOL set. U
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21. Parallel Packet Switch Results
If S > 2 then each cell is guaranteed to find a layer that belongs to both the AIL and AOL sets.
If S > 2 then a PPS can precisely emulate a FIFO output queued switch for all traffic patterns.
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22. Precise Emulation of an OQ Switch
Yes No =? R
PPS
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23. Parallel Packet Switch Results
If S > 3 then a PPS can precisely emulate an OQ switch with WFQ or strict priorities for all traffic patterns.
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24. Is this Practical ? NO There are two reasons: 1) Maintaining
AIL - That is easy.
AOL - That is not.
2) Packet order is decided by the output.
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25. A Practical Distributed Algorithm
If S > 2 then a PPS with distributed AOL can precisely emulate a FIFO output queued switch for all traffic patterns. The PPS will have a fixed latency of Nk/S time slots.
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26. Conclusions
Its possible to design a high speed single stage packet switch from multiple slower speed packet switches.
Such a switch can emulate an OQ switch.
There remain a couple of open questions
Making QoS practical.
Making multicasting practical.
This is just the first step towards scaleable switch fabrics.
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