1. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Chapter 5 MOS Capacitor
MOS: Metal-Oxide-Semiconductor Vg Vg
gate
metal
gate
SiO2
SiO2 N+ N+
Si body
P-body
MOS transistor
MOS capacitor
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

2. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Chapter 5 MOS Capacitor
Ef , Ec Ev
Si Body
Gate Ec Ef n o y c d i l o i b s 2 y O n l i o o S c p i + i l N S - P
This energy-band diagram for Vg = 0 is not the simplest one.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

3. 5.1 Flat-band Condition and Flat-band Voltagec
=0.95 eV
SiO 2 E c q y g c q y = c
+ ( E – E )
3.1 eV
3.1 eV Si s Si c f
=4.05eV E E E c , f V c q fb E E f v E v N +
-poly-Si
9 eV
P-body
The band is flat at the flat band voltage.
E0 : Vacuum level
E0 – Ef : Work function
E0 – Ec : Electron affinity
Si/SiO2 energy barrier
4.8 eV E v
SiO 2
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

4. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.2 Surface Accumulation
Make Vg < Vfb
3.1eV E c , f v M O S qV g V ox q s
fs : surface potential, band bending
Vox: voltage across the oxide
is negligible when
the surface is in accumulation.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

5. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.2 Surface Accumulation
Vg <Vt
Gauss’s Law
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

6. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.3 Surface Depletion ( ) g V
> fb E c , f v M O S qV g
depletion
region q s W
dep ox -
SiO 2
gate
P-Si body V
depletion layer
charge, Q
dep
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

7. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.3 Surface Depletion
This equation can be solved to yield fs .
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

8. 5.4 Threshold Condition and Threshold Voltage, f M O S v i A B C = q D qV g t st
Threshold (of inversion):
ns = Na , or
(Ec–Ef)surface= (Ef – Ev)bulk , or
 A=B, and C = D
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

9. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Threshold Voltage ox s fb g V φ + =
At threshold,
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

10. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Threshold Voltage
+ for P-body,
– for N-body
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

11. 5.5 Strong Inversion–Beyond Threshold
Vg > Vt E c , f v M O S qV g -
SiO 2
gate P -
Si substrate V g
> t Q
dep
inv
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

12. Inversion Layer Charge, Qinv (C/cm2)
Vg > Vt
Vg > Vt
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

13. 5.5.1 Choice of Vt and Gate Doping Type
Vt is generally set at a small positive value so that, at Vg = 0, the transistor does not have an inversion layer and current does not flow between the two N+ regions
P-body is normally paired with N+-gate to achieve a small positive threshold voltage.
N-body is normally paired with P+-gate to achieve a small negative threshold voltage.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

14. Review : Basic MOS Capacitor Theoryfs
2fB Vg
Vfb Vt
accumulation
depletion
inversion
Wdep W
dmax W
= (2 e 2 f / q N )
1/2
dmax s B a ( f )
1/2 s Vg
Vfb Vt
accumulation
depletion
inversion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

15. Review : Basic MOS Capacitor Theory
Qdep=- qNaWdep
Vfb
total substrate charge, Qs
accumulation
depletion
inversion Vg
(a) Vt
–qNaWdep
–qNaWdmax
Qinv Qs
accumulation
depletion
inversion
accumulation
depletion
inversion Vg
regime
regime
regime
(b)
Vfb Vt
slope = - Cox
Vfb Vg Vt
Qacc
Qinv
slope = - Cox
(c)
slope = - Cox
Vfb Vt Vg
accumulation
depletion
inversion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

16. 5.6 MOS CV Characteristics
C-V Meter
MOS Capacitor
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

17. 5.6 MOS CV CharacteristicsQs
accumulation
depletion
inversion C
regime
regime
regime
Cox
Vfb Vg Vt
Qinv Vg
slope = - Cox
Vfb Vt
accumulation
depletion
inversion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

18. CV Characteristics In the depletion regime: C Cox Vg Vfb Vt
accumulation
depletion
inversion Vg
Vfb Vt
In the depletion regime:
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

19. Supply of Inversion Charge May be Limited+ C ox
gate
P-substrate -
dep
Wdep
Accumulation
Depletion C ox
gate
P-substrate -
- -
dmax W AC DC
gate C ox N + - - - - - - - -
Inversion
Wdmax
Inversion
DC and AC
P-substrate
In each case, C = ?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

20. Capacitor and Transistor CV (or HF and LF CV)
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

21. Quasi-Static CV of MOS Capacitor
Cox
accumulation
depletion
inversion Vg
Vfb Vt
The quasi-static CV is obtained by the application of a slow linear- ramp voltage (< 0.1V/s) to the gate, while measuring Ig with a very sensitive DC ammeter. C is calculated from Ig = C·dVg/dt. This allows sufficient time for Qinv to respond to the slow-changing Vg .
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

22. EXAMPLE : CV of MOS Capacitor and TransistorVg
QS CV
HF capacitor CV
MOS transistor CV,
Does the QS CV or the HF capacitor CV apply?
(1) MOS transistor, 10kHz.            (Answer: QS CV).
(2) MOS transistor, 100MHz.         (Answer: QS CV).
(3) MOS capacitor, 100MHz.         (Answer: HF capacitor CV).
(4) MOS capacitor, 10kHz.            (Answer: HF capacitor CV).
(5) MOS capacitor, slow Vg ramp.   (Answer: QS CV).
(6) MOS transistor, slow Vg ramp.   (Answer: QS CV).
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

23. 5.7 Oxide Charge–A Modification to Vfb and Vt
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

24. 5.7 Oxide Charge–A Modification to Vfb and Vt
Types of oxide charge:
Fixed oxide charge, Si+
Mobile oxide charge, due to Na+contamination
Interface traps, neutral or charged depending on Vg.
Voltage/temperature stress induced charge and traps--a reliability issue
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

25. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
EXAMPLE: Interpret this measured Vfb dependence on oxide thickness. The gate electrode is N+ poly-silicon.
–0.15V
–0.3V
Tox
Vfb
10 nm
20 nm
30 nm
What does it tell us? Body work function? Doping type? Other?
Solution:
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

26. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
from intercept E
, vacuum level f , c v y g s =
+ 0.15V N +
-Si gate
Si body
N-type substrate,
from slope
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

27. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.8 Poly-Silicon Gate Depletion–Effective
Increase in Tox
Gauss’s Law
poly ox
dpoly qN W / E e = P+
If Wdpoly= 15 Å, what is the
effective increase in Tox?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

28. Effect of Poly-Gate Depletion on Qinv
Poly-gate depletion degrades MOSFET current and circuit speed. W
dpoly E c
How can poly-depletion be minimized? E , E f v q f
poly E c E f E v P +
-gate
N-substrate
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

29. EXAMPLE : Poly-Silicon Gate Depletion
Vox , the voltage across a 2 nm thin oxide, is –1 V. The P+ poly- gate doping is Npoly = 8 1019 cm-3 and substrate Nd is 1017cm-3. Find (a) Wdpoly , (b) fpoly , and (c) Vg .
Solution:
(a) nm 3 . 1 8 C 10 6 cm 2 V )
F/cm ( 85 9 / 19 7 14 = -
poly ox
dpoly qN T W e E
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

30. EXAMPLE : Poly-Silicon Gate Depletion
(b)
(c)
Is the loss of 0.11 V from the 1.01 V significant?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

31. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.9 Inversion and Accumulation Charge-Layer
Thickness–Quantum Mechanical Effect
Average inversion-layer location below the Si/SiO2 interface is
called the inversion-layer thickness, Tinv .
-50
-40
-30
-20
-10 10 20 30 40 A 50
Tinv Si
Gate
Effective T ox
Physical
n(x) is determined by Schrodinger’s eq., Poisson eq., and Fermi function.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

32. Electrical Oxide Thickness, Toxe
Tinv is a function of the average electric field in the inversion layer, which is (Vg + Vt)/6Tox (Sec ).
Tinv of holes is larger than that of electrons because of difference in effective mass.
Toxe is the electrical oxide thickness.
at Vg=Vdd
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

33. Effective Oxide Thickness and Effective
Oxide Capacitance 3 /
inv
dpoly ox
oxe T W + = C
Basic CV
with poly-depletion
with poly-depletion and
charge-layer thickness Vg
measured data ox
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

34. Equivalent circuit in the depletion and the inversion regimes
(b)
(c)
(d)
General case for both depletion and inversion regions.
In the depletion regions
Vg  Vt
Strong inversion
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-34 34

35. 5.10 CCD Imager and CMOS Imager
Deep depletion, Qinv= 0
Exposed to light
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

36. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
CCD Charge Transfer
P-Si
oxide V2 -
depletion region
(a)
(b)
(c)
V1 > V2 = V3 V1 V3
V2 > V1 > V3
V2 > V1 = V3
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

37. two-dimensional CCD imager
Signal out
Charge-to-voltage converter
Reading row, shielded from light
The reading row is shielded from the light by a metal film. The 2-D charge packets are read row by row.
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-37 37

38. CMOS Imager
PN junction charge collector
switch
Amplifier circuit
Shifter circuit
Signal out V2 V1 V3
CMOS imagers can be integrated with signal processing and control circuitries to further reduce system costs. However, The size constrain of the sensing circuits forces the CMOS imager to use very simple circuits
Modern Semiconductor Devices for Integrated Circuits (C. Hu)
Slide 5-38 38

39. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.11 Chapter Summary
N-type device: N+-polysilicon gate over P-body
P-type device: P+-polysilicon gate over N-body
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

40. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.11 Chapter Summary or
+ : N-type device, – : P-type device
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

41. 5.11 Chapter Summary What’s the diagram like at Vg > Vt ? at Vg= 0?
N-type Device
(N+-gate over P-substrate)
P-type Device
(P+-gate over N-substrate)
What’s the diagram like at Vg > Vt ? at Vg= 0?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)

42. Modern Semiconductor Devices for Integrated Circuits (C. Hu)
5.11 Chapter Summary
What is the root cause of the low C in the HF CV branch?
Modern Semiconductor Devices for Integrated Circuits (C. Hu)