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Dueling Segmented LRU Replacement Algorithm

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Presentation on theme: "Dueling Segmented LRU Replacement Algorithm"— Presentation transcript:

1 Dueling Segmented LRU Replacement Algorithm
Hongliang Gao Chris Wilkerson

2 The Basic Ideas Auxiliary Directory: Segmented LRU list:
Evaluates “dueling” replacement algorithms. Segmented LRU list: Reference bit protects lines with good locality. Aging/ Random Promotion. Adaptive Bypass: Protect cache contents by bypassing the cache completely.

3 Dueling Replacement Algos
32 sets sampled (static) 2 policies evaluated in each sampled set. 16-bit mini-tags Counter updated when policies differ. Auxiliary Directory Set0 Set1 Set2 Set3 Set4 Set5 Set6 Set7 Saturating Counter Tag Array

4 Review of Segmented LRU
SLRU: Reference Bit 4 LRU bits per line track LRU position Tag Reference bit is marked when a line is referenced. Replace any non-referenced lines first. Replace global LRU if all lines are referenced.

5 SLRU Features Random Promotion Aging
Reference bit is marked when referenced or when randomly promoted. Eg: 1/32 newly allocated lines may randomly be selected for promotion. Aging Reference bits can be cleared as well as set. Line allocations cause the reference bit of the LRU line to be cleared.

6 Adaptive Bypass Misses result in allocation or bypass.
Thrashing on 4th way No Thrashing Data Structure w/o Bypass w/ Bypass Cache Bypass based on a random probability. Eg: 1, 1/2, 1/4, … 1/4096. Probability is doubled/halved according to the success of previous bypasses.

7 SLRU w/ Adaptive Bypassing
SLRU: Reference Bit De-allocated line tracked by partial tag. Allocated line tracked by 4 bit pointer. Valid Bit Virtual Bypass Bit 1 1 16 bit partial tag for “out-of-cache” competitor 4 bit pointer for “in-cache competitor”

8 Frequency of Bypass

9 DSB impact on MPKI vs TLRU
MPKI for true LRU % reduction MPKI w/ DSB

10 Speedup

11 BACKUP

12 SLRU w/ Adaptive Bypassing
SLRU: Reference Bit Bypass Bypassed line tracked by partial tag. Incumbent line tracked by 4 bit pointer. Subsequent reference to bypass line reduces bypass probability. Subsequent reference to incumbent increases bypass probability. 1 16 bit partial tag for “out-of-cache” competitor 4 bit pointer for “in-cache competitor”

13 Config2: 2 Policies CONFIG 1 2 3 Enable bypassing for policy0 True
False Random promotion probability for policy0 Random promotion probability for policy1 16 Aging for policy0 Aging for policy1 Virtual bypassing probability 8 Initial bypassing probability 64 Second minimum bypassing probability (minimum is 0) 1/256 1/4096 Config2: 2 Policies

14 4 LRU bits per line track LRU position
auxiliary directory collects statistics replacement policy performance and updates a policy selector counter. SLRU 1-reference bit indicates whether each line is in the reference or non-reference list. Set0 Set1 Set2 Set3 Set4 Set5 Set6 Set7 4 LRU bits per line track LRU position Tracking bypass valid bits Tag Array 16 bit partial tag for “out-of-cache” competitor 4 bit pointer for “in-cache competitor”


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