1. SD1020 Number of Members :3 Vidura Manu Wijayasekara Ridhima Agarwal Bhaskar Kumar Advisor : Dr. Sudarshan Srinivasan

2. THE FIVE CLASSIC COMPONENTS OF A COMPUTER
Input,output,momory,datapath and control. The last two sometimes combine and called the processor.

3. 32-Bit MIPS Elastic Synchronous Processor

4. INTRODUCTION In this project we would implement a synchronous processor, which is latency insensitive by design. Many research is happening in the industry on this topic, since the timing issues get more harder to solve with wire delays becoming an significant factor. In current method wire delays cannot be determined until final layout, which is a significant draw back in the synchronous design phase.

5. LATENCY

6. As the size of the transistor gets smaller… -Gate delay improves -Wire delay becomes too large to ignore
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate
Logic Gate

7. WIRE DELAY CANNOT BE DETERMINED UNTIL THE FINAL LAYOUT

8. REQUIREMENTS
Study the MIPS (Microprocessor without Interlocked Pipeline Stages) architecture
Test with two benchmarks to verify the functionality of the processor
Study Synthesis of Synchronous Elastic Architectures and implement on a MIPS processor.
Compile, simulate, test, and verify each component on the DE2 development board with the Altera Cyclone II FPGA.
Design controllers for Latency Insensitive Design.

9. TECHNICAL CONTENT DESIGN APPROACH CURRENT DESIGN COMPONENTS PIPELINING
ELASTIC CONTROLLERS
TESTING, EVALUATION, AND VERIFICATION
SOFTWARE IMPLEMENTATION

10. DESIGN APPROACH The logic design is described using VHDL
Will be tested on Altera Cyclone II FPGA
The project is in two phases:
Phase 1: a synchronous microprocessor will be designed and implemented.
Phase2: the design will be modified to a latency insensitive microprocessor and implemented

11. COMPONENTS ALU Program Counter Instruction Memory Data Memory
Registers & Register File
Decoder
Forwarding Unit
Hazard Detection Unit
Elastic Controllers

12. ALU (Arithmetic Logic Unit)
Does the major calculations including add, AND, OR sub
In MIPS, the ALU takes two 32-bit inputs and produces one 32-bit output, plus some additional signals.

13. Final 32-Bit ALU

14. Program Counter (PC)
The register containing the address of the instruction in the program being executed.
MIPS instructions are each four bytes long, so the PC should be incremented by four to read the next instruction in sequence.

15. Instruction Memory (IM)
Holds the instructions of a program.
This design is capable of four basic instructions:
R type Instructions
(includes all the ALU operations)
Load/Store Instructions
Load: read a value from a memory location
Store: write a value to a memory location
Branch if equal Instruction
Branch to a given offset if two register
values are equal.

16. Instruction Fetch Stage

17. Data Memory
A 32-bit register file being used for the data memory for simplicity.
This model contains only 128 bytes of memory.

18. Registers AND Register File
Register File: A state element that consists of a set of registers that can be read and written by supplying a register number to be accessed.
Registers: Small, fast, storage units that are a part of the data path of the computer.
Size: from a few bits to a few hundred bits. MIPS registers hold 32 bits.
Number: from one to a few hundred. MIPS has 32 registers.

19. Decoder
A logic block that has an n-bit input and 2n outputs where only one output is asserted for each input combination
Block diagram of MIPS decode unit

20. Forwarding Unit
A method of resolving the data hazard by retrieving from internal buffers rather than waiting for it to arrive from programmer-visible registers or memo
Hazard Detection Unit
This operates in the ID stage.
Handles the data and control hazards created by the Forwarding unit.
It stalls or flushes the registers to prevent unpredictable operations.

21. Final Datapath before Pipelining

22. Pipelining Buffered, Synchronous pipelines
Conventional microprocessors are synchronous circuits that use buffered, synchronous pipelines. In these pipelines, "pipeline registers" are inserted in-between pipeline stages, and are clocked synchronously. The time between each clock signal is set to be greater than the longest delay between pipeline stages, so that when the registers are clocked, the data that is written to them is the final result of the previous stage.

23. Pipelined Datapath

24. Elastic Controllers
For Latency Insensitivity, the latches in the pipeline will be replaced with Elastic Controllers.
This will be done in the next semester.

25. TESTING, EVALUATION AND VERIFICATION
Each component has been separately tested on Altera (FPGA).
The functionality of each component is further evaluated on the FPGA and the data or the output after performing the test have been collected.
The verification of the data/output has been done.

26. EVALUATION OF THE PIPELINE Executed instruction: 000000 00001 00011 00011 00000 100000
1st cc
2nd cc
3rd cc
4th cc
5th cc
6th cc
7th cc
8th cc
9th cc
REG03 1 2 3 4 5
IF/ID
... …. …
ID/EX
EX/
MEM
MEM/WB

27. Software Implementation
Why Software is needed: Hardware doesn’t execute MIPS assembly language code. It only stores and executes those instructions that are written in a suitable format. This binary format is called the Machine Language.
Software chosen:
Machine Language: As it can be used directly by the hardware for execution.
Assembly Language: Since machine code is very hard to understand that is why it is needed to make it understandable and human-centric. For this, Assembly Language is selected as it is very close to Machine code.

28. Instructions Performed
ALU Instructions: ADD , AND , OR , SUB , SLT , J
 OP Code( it is of 6 bits of length)
 1St Register( 5 bits of address length)
2ND Register( 5 bits of address length)
16 bits of number to be performed with 2ND register.
ALU Instruction
Op Code
ADD
001000
AND
100100 OR
100101
SUB
100010
SLT
101010 J
000010

29. BUBBLE SORTING

30. LINEAR SEARCH

31. PROJECT STATUS
The first phase of the project has been achieved successfully.
This second phase will be resumed starting from Spring 2011.
Some work is already being done for the second phase.(Elastic Controllers)

32. UPDATED TIMELINE First Group Meeting 2 All Requirements Capture 3
SL.NO
TASKS
DURATION ( weeks)
Person Responsible 1
First Group Meeting 2
All
Requirements Capture 3
Adder & Subs tractor
ALU instruction program for MIPS in Asm 4
Rid-Vid, Bhaskar
ALU (Operations+ Unit)
Encode programs in machine code
4,5 5
Implement Pipeline
Algorithm for Linear Search
5,6 6
Decoding Logic
Algorithm for Sorting
6,7 7
Program Counter Logic
Asm for Linear search
6,8 8
ALU Instructions
Asm for linear sorting
7-9,9 9
Load Instructions
Encoding Linear Search
9-11,10 10
Store Instructions
Encode Sorting 11
Branch Instructions, EC
Test Sorting
12-14,12 12
FPGA test
Test Binary search Program
15,13-15 13
Presentation + Demo 16

33. “COMPUTER ORGNIZATION AND DESIGN”
BUDGET
ITEM
DISCRIPTION
AMOUNT($)
BOOK
“COMPUTER ORGNIZATION AND DESIGN”
50.00
TOTAL
APPROVED BUDGET

34. SUMMARY
The Synchronous Latency Insensitive is an effective design which can resolve the timing issues.
The software segment holds a vital importance in the verification of the final design.
So far we were able to accomplish our target and look towards the upcoming semester.