1. CHAPTER 6 INPUT/OUTPUT PROGRAMMING
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

2. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Relative Speed
I/O devices are sometimes mechanical devices (e.g., solenoids, relays, etc.) that take a long time to perform an action.
The computer performs operations orders of magnitude faster than the I/O devices.
Synchronization: The CPU must wait for the I/O device to finish each command before issuing the next.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

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Asynchronous Events
The events that determine when an input device has data available or when an output device needs data are independent of the CPU.
Most I/O programming, therefore, requires "hand-shaking" between the CPU and the I/O device to coordinate the transfer so that data is transferred reliably.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

4. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Time Behavior
Data Rate
Pattern
Increasing Time 
Low
Random
      
Periodic
            
High
  
   
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

5. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Three Strategies
Polled Waiting Loops
Interrupt-driven I/O
Direct Memory Access (DMA)
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

6. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Selecting a Strategy
Maximum Data Transfer Rate
Worst-case Response Time (Latency)
Cost (Hardware)
Software Complexity
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

7. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Polled Waiting Loop
Interrupt-Driven
Direct Memory Access
Maximum Transfer Rate
Slowest
Fastest
Worst-Case Latency
Unpredictable
Best
Hardware Cost
Least
Low
Moderate
Software Complexity
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

8. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Polled Waiting Loops
BYTE8 Input(void) { while ((inportb(STATUS_PORT) & READY) == 0) { /* wait for new data to arrive */ } return inportb(DATA_PORT) ; }
void Output(BYTE8 ch) { while ((inportb(STATUS_PORT) & READY) == 0) { /* wait for device to finish last command */ } outportb(DATA_PORT, ch) ; }
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

9. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Polled Serial Input
_Serial_Input:
MOV DX,02FDh ; DX  Status Port Address
SI1: IN AL,DX ; Read Input Status Port
TEST AL, B ; Check the “Ready” Bit
JZ SI1 ; Continue to wait if not ready
MOV DX,02F8h ; Else load DX with Data Port Address
XOR EAX,EAX ; Pre-clear most significant bits of EAX
IN AL,DX ; Read Data Port
RET ; return to caller with data in EAX
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

10. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Polled Waiting Loops
Test device status in a waiting loop before transferring each data byte.
Maximum data rate: Time required to execute one iteration of the waiting loop plus the transfer.
Latency: Time from device ready until the moment that the CPU transfers data. Unpredictable - no guarantee when the program will arrive at the waiting loop.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

11. Estimating Performance
Performance limited by memory bandwidth (bytes/second):
Typical memory cycle time  60 ns = 60  10-9 sec.
Determines how fast instructions can be fetched.
We ignore speedup due to cache, so estimate is pessimistic.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

12. 14 instruction bytes, 4 stack bytes, 2 I/O transfers
Memory and I/O Cycles
; Opcode Immediate Stack I/O _Serial_Input: ; Bytes Bytes Bytes Transfers MOV DX,02FDh ; 1 2 SI1: IN AL,DX ; TEST AL, B ; JZ SI1 ; MOV DX,02F8h ; XOR EAX,EAX ; 1 IN AL,DX ; RET ; 1 4
14 instruction bytes, 4 stack bytes, 2 I/O transfers
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

13. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Memory Cycles
14 instruction bytes  4 bytes/memory read = 4 memory cycles (minimum) = 240 ns.
4 stack bytes  4 bytes/memory read = 1 memory cycle (minimum) = 60 ns.
Code and stack in different parts of memory
Address alignment may increase cycle counts.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

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I/O Cycles
Assume 33 Mhz PCI bus: s per I/O read or write = 30 ns (Actual I/O transfers usually requires multiple I/O bus cycles.)
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

15. Maximum Data Rate (Polled Waiting Loop)
Time for one iteration of waiting loop plus subsequent I/O transfer:
memory cycles: 300 ns
I/O cycles: 60 ns
total time: 360 ns
maximum data rate = 1/360 ns per byte
= 2.78 MB/Sec
Fastest serial I/O:
= 115,000 bps
 10 KB/Sec.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

16. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Interrupt-Driven I/O
Hardware interrupt request occurs: CPU finishes the current instruction and then initiates an interrupt response sequence.
Interrupt Response Sequence: CPU pushes flags and return address, disables interrupts, reads an interrupt type code from the requesting device, and transfers control to the corresponding Interrupt Service Routine.
Interrupt Service Routine:
1. Re-enable higher priority interrupts.
2. Preserve CPU registers.
3. Transfer data (also clears the interrupt request).
4. Re-enable lower priority interrupts.
5. Restore CPU registers.
6. Pop flags and return address and return to interrupted code.
Interrupt Complete: Interrupted code continues where it left off as if nothing happened.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

17. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Getting Address of ISR
IDTR Register
Interrupt Descriptor Table
Resides in Main Memory
Address (& Length) of IDT
32 bits +
Physical Address of ISR
32 bits x 8
8 bits
Interrupt Type Code
Index into IDT
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

18. Hardware Response to Interrupt
Action
Detailed description
Bytes Transferred
1. Push EFlags register.
ESP  ESP - 4; MEM32[ESP]  EFlags
4 (stack write)
2. Disable interrupts.
IF Flag  0 (Also clears TF Flag)
n/a
3. Push CS
ESP  ESP - 4; MEM32 [ESP]  CS
4 (stack write)
3. Push EIP
ESP  ESP - 4; MEM32 [ESP]  EIP
4 (stack write)
4. Identify interrupt.
Read interrupt type code from data bus.
1 (I/O read)
5. Load CS and EIP
CSvisible,EIP  IDT64[8  int. type code]
CShidden  GDT64[CSvisible]
8 (IDT read) +
8 (GDT read)
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

19. Interrupt-Driven Latency
Time to finish longest instruction
Time of hardware response
Time in ISR until data is transferred.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

20. Time of Longest Instruction
PUSHA:stores contents of 8 registers by pushing their contents onto the stack.
Requires 1 memory cycle to fetch the 1‑byte representation of the instruction and 8 memory cycles to write 32 bytes to memory.
Total time: 0.54 µs
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

21. Hardware Response to Interrupt
29 bytes of data to be transferred:
12 stack bytes: (3 mem cycles = 180 ns)
1 I/O byte: (1 I/O cycle = 30 ns)
8 IDT to CS & EIP: (2 mem cycles = 120 ns)
8 GDT bytes to hidden part of CS: (2 mem cycles = 120 ns)
Total time: 450 ns = 0.45 µs
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

22. Time from ISR Entry to Transfer
  Instr. Data Stack I/O _Serial_Input_ISR: Bytes Bytes Bytes Transfers
STI ; Enable high prior. Ints. 1 PUSH EAX ; Preserve contents PUSH EDX ; of EAX and EDX MOV DX,02FDh ; Retrieve the data and 3 IN AL,DX ; clear the request MOV [_serial_data],AL ; Save the data away MOV AL, b ; Send EOI command to 2 OUT 20h,AL ; Prog. Interrupt Ctlr POP EDX ; Restore orig. contents POP EAX ; of the registers IRET ; Restore EIP and EFlags
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

23. Time from ISR Entry to Transfer
Bytes Cycles Code 7 2 Data 0 0 Stack 8 2
Memory: 4 x 60ns = .24 µs I/O: 1 x 30ns = .03 µs Total: 0.27 µs
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

24. Interrupt-Driven Latency
Time to Execute Longest Instruction
PUSHA: 0.54 µs
Hardware Response
0.45 µs
Time from Entry of the ISR through the I/O Data Transfer
0.27 µs
Latency to IN AL,DX = 1.26 µs
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

25. Interrupt-Driven Data Rate (1 / Time Per Transfer)
Time to finish longest instruction
Time of hardware response
Time to execute entire ISR
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

26. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Total Time in ISR
  Instr. Data Stack I/O _Serial_Input_ISR: Bytes Bytes Bytes Transfers
STI ; Enable high prior. Ints. 1 PUSH EAX ; Preserve contents PUSH EDX ; of EAX and EDX MOV DX,02FDh ; Retrieve the data and 3 IN AL,DX ; clear the request MOV [_serial_data],AL ; Save the data away MOV AL, b ; Send EOI command to 2 OUT 20h,AL ; Prog. Interrupt Ctlr POP EDX ; Restore orig. contents POP EAX ; of the registers IRET ; Restore EIP and EFlags
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

27. Total Time in ISR Bytes Cycles Code 19 5 Data 1 1 Stack 28 7
Memory: 13 x 60ns = .78 µs I/O: 2 x 30ns = .06 µs Total: 0.84 µs
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

28. Maximum Data Rate = 1/1.95 µs = 0.513 MB/Sec
Total Time Per Byte
Time to Execute Longest Instruction
Hardware Response
Time to Execute the entire Interrupt Service Routine
PUSHA: 0.54 µs
0.45 µs
0.84 µs
Total time per transfer = 1.95 µs
Maximum Data Rate = 1/1.95 µs = MB/Sec
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

29. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Estimate Summary
Worst-Case Latency
Maximum Data Rate
Polled Waiting Loop
Unpredictable
2.78 MB/Sec
Interrupt-Driven
1.26 µs
0.513 MB/Sec
DMA ?
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

30. Programmable Interrupt Controller
Interrupt Type Code
8259A Programmable Interrupt Controller
"In‑Service" Register
Interrupt Acknowledge
Interrupt Request
CPU data bus
CPU
8 Interrupt Request Lines from I/O devices
"Mask" Register
IRQ0
IRQ1
IRQ7
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

31. Programmable Interrupt Controller
External device requests service by setting its IRQ line to 1.
Request is forwarded to CPU if corresponding mask bit is zero and no higher priority interrupt is in progress.
If IF=1, CPU sends interrupt acknowledge to PIC, reads interrupt type code, causing PIC to set “in service” bit, disabling lower priority interrupts.
Non-Specific “end of interrupt” (EOI) at end of ISR clears “in service” bit.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

32. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Buffering
dequeue position (front)
q.bfr P L E A S O G I N : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
enqueue position (rear) 20
q.size
q.count 17
q.nq 4
q.dq 13
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33. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
EXTERN _q ; QUEUE *q
_COM1InISR:
STI ; re-enable higher priority interrupts
PUSHA ; save general-purpose registers
PUSH DS ; save segment registers
PUSH ES
PUSH FS
PUSH GS
XOR EAX,EAX
IN AL,02FDh ; read COM1 data port
PUSH EAX ; pass data to Q
PUSH _q ; pass pointer to Q
CALL _Enqueue ; Enqueue the data
ADD ESP,8 ; remove parameters
MOV AL, B ; re-enable lower
OUT 20H,AL ; priority interrupts
POP GS ; restore segment registers
POP FS
POP ES
POP DS
POPA
IRET
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

34. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Direct Memory Access
Requires additional hardware to control data transfers independent of CPU.
Competes with CPU for control of the bus.
Does not have to wait for current instruction to complete – only the current bus operation.
Latency is thus 1 memory cycle.
Data Rate determined by memory speed.
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

35. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Estimate Summary
Worst-Case Latency
Maximum Data Rate
Polled Waiting Loop
Unpredictable
2.78 MB/Sec
Interrupt-Driven
1.26 µs
0.513 MB/Sec
DMA
0.06 µs
66.7 MB/Sec
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.

36. Copyright © 2000, Daniel W. Lewis. All Rights Reserved.
Single Buffering
DMA Write
CPU Read
Double Buffering
DMA Write Buffer 1
DMA Write Buffer 2
CPU Read Buffer 1
CPU Read Buffer 2
Copyright © 2000, Daniel W. Lewis. All Rights Reserved.