1. LO and Clock Generation and Distribution: LO Box and LO Splitter Box
CDR of LLRF for Warm Linac
January 15, 2019, ESS, Lund
Pedro González
Arash Kaftoosian

2. LLRF CDR, ESS, Lund, January 2019
Outline:
LO/CLK BOX PROTOTYPE AT ESS-BILBAO
PROJECT DESCRIPTION
Scope
LO/CLK Distribution
LO Box
LO Splitter Box
TECHNICAL SPECIFICATIONS
LO Box specifications
LO Splitter Box Specifications
Risk Management
CONCLUSION AND NEXT STEPS
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LLRF CDR, ESS, Lund, January 2019

3. LO/CLK Box Prototype developed and tested at ESS-Bilbao
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LLRF CDR, ESS, Lund, January 2019

4. LLRF CDR, ESS, Lund, January 2019
LO/CLK Box Prototype
Two LO/CLK box prototypes were developed and tested at ESS-Bilbao:
One based on LMX2582 PLL RF synthesizer
And one based on divide-and-mix topology
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

5. LLRF CDR, ESS, Lund, January 2019
LO/CLK Box Prototype
Reference signal used for the tests
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

6. Test results: LO Amplitude stability LO Phase Noise
LO OUTPUT
Specification
Measurement
Comment
LO frequency range …
/11
SSB Phase Noise L(f)
(dBc/Hz)
@ 10 Hz:
-96
@ 100 Hz:
-107
@ 1 kHz:
-124
@ 100 kHz: -123
-133
@ 100 kHz: -141
-135
Limited by reference used
@ 1 MHz:
-144
@ 10 MHz: -170
-153
Limited by reference and possibly by divider floor
Jitter/Integrated phase noise, additive
200 fsec rms (10 Hz to 1 MHz)
100
(10 Hz to 10 MHz)
LO Phase Noise
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

7. Test results: LO Close in carrier spurs Near carrier spurs Harmonics
Harmonics and Spurious for LO output
LO OUTPUT
Specification 352 MHz
Measurement
Comment
Harmonics
< -50 dBc (<= 3xLO)
< -60 dBc for (> 3xLO)
< -71 dBc
< -75 dBc ok
Spurious
< -80 dBc (> 1 MHz)
< 10 dB above PN limits (10 kHz-1 MHz)
< 5 dB above PN limits (<=10 kHz)
< -85 dBc ( Hz) < -100 dBc ( Hz)
<-80 dBc others
Related to reference and mains
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LLRF CDR, ESS, Lund, January 2019

8. LLRF CDR, ESS, Lund, January 2019
Test results: Clock
The MHz reference is divided by 3 to generate the clock at MHz using a low noise divider/prescaler and a low jitter LVPECL fanout buffer to provide 6 clock outputs. A low-pass filter is inserted after the divider, to reduce higher order harmonics and shape a proper square signal at 117 MHz for the LVPECL fanout buffer.
Phase Noise of Clock Output 1 (LVPECL), 352 MHz reference divided by 3
Spectrum of Clock Output 1 (LVPECL)
Long term Clock stability
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LLRF CDR, ESS, Lund, January 2019

9. LLRF CDR, ESS, Lund, January 2019
PROJECT DESCRIPTION
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LLRF CDR, ESS, Lund, January 2019

10. LLRF CDR, ESS, Lund, January 2019
Scope
The scope includes 10 LO/Clock generator boxes and one LO/Clock splitter box to feed the LLRF systems for the RFQ, MEBT buncher cavities, DTL tanks and spoke cavities.
Each RTM/AMC card in LLRF module needs one LO signal and one CLK for signal down-conversion and digitalization, as well as a reference signal at MHz for up-conversion using a vector modulator
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LLRF CDR, ESS, Lund, January 2019

11. LLRF CDR, ESS, Lund, January 2019
Scope
352 MHz Section
Section
RFQ
MEBT
DTL
Spoke
Number of LLRFs 1 3 5 26
Number of RTM/AMC per LLRF 4
LO/CLK required 15
There will be 35 LLRF modules along the 352 MHz section with a total amount of 48 RTM/AMC cards, hence 48 LO signals and 48 CLK signals will be required.
Each LO box has 4 LO outputs and 4 CLK outputs. To feed all 35 LLRFs (48 RTM/AMC cards), 10 LO boxes and one splitter box will be required.
The same LO system can be used for beam instrumentation such as the BPMs for the 704 MHz section, which operates at 352 MHz
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

12. LLRF CDR, ESS, Lund, January 2019
LO/CLK Distribution
Separate LO boxes are to be used for RFQ, MEBT bunchers and for each spoke section cryomodule (comprising 4 cavities). For DTL tanks, one LO box and one splitter will be used.
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

13. LLRF CDR, ESS, Lund, January 2019
LO Box
LO box will be developed based on a direct analog synthesizer or “Divide-and- Mix” topology.
Each LO box will provide 4 identical LO outputs and 4 CLK outputs and should be equipped with monitoring/control interfaces.
Although at the moment, interlock interfaces are not foreseen to be used, but two signals (enable/disable and ready/fault) will be considered for potential future needs.
A total amount of 10 LO boxes will be developed, according to this design, by using surface mount components, preferably all on one common PCB. Careful measures must be taken to avoid cross-talk and interference between components across the board.
Next slide shows block diagram of the LO box prototype based on divide-and- mix design.
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LLRF CDR, ESS, Lund, January 2019

14. LLRF CDR, ESS, Lund, January 2019
LO Box Block Diagram
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LLRF CDR, ESS, Lund, January 2019

15. LO Splitter Box Block Diagram
One LO box will be used for DTL section which comprises 5 tanks. Each tank has one LLRF module with 3 RTMs/AMCs. Therefore, a total amount of 15 LOs/CLKs are needed for the DTL section.
That would require 4 LO boxes, but it has been decided to use one LO box for the DTL section, hence a splitter box to split 4 LOs and 4 CLKs (outputs of one LO box), to 15 LOs and 15 CLKs will be developed.
This splitter will be an active unit including amplifiers, filters, power dividers, fanout buffers, etc., using as much as possible the same components/design of the LO box.
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LLRF CDR, ESS, Lund, January 2019

16. LLRF CDR, ESS, Lund, January 2019
TECHNICAL SPECIFICATIONS
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LLRF CDR, ESS, Lund, January 2019

17. LO Box Specs Square wave, or Sine wave, That is the question!!
LO OUTPUT
No. Outputs 4
Power Level
15 dBm ±1 dB (sine wave)
Return Loss
> 14 dB (50 ohm)
LO frequency range
MHz ( ÷11)
MHz ( ÷14)
SSB Phase Noise L(f) (dBc/Hz)
< 10 Hz
< 100 Hz
< 1 kHz
< 10 kHz
< 100 kHz
< 1 MHz
< 10 MHz
Jitter/Integrated phase noise
< 80 fsec rms (10 Hz to 1 MHz)
Harmonics
< -60 dBc
Spurious
< -70 dBc (Offsets > 1 MHz)
Amplitude unbalance
< 0.3 dB, peak to peak, between outputs
Phase unbalance
< 5 deg, peak to peak, between outputs
LO output variation due to ref input level change
< 0.3 dB/dB
LO output variation due to temperature
< 0.05 dB/degC, over the operating temperature range
CLOCK OUTPUT
Clock frequency range
MHz (352.21÷3)
MHz (352.21÷4)
No. Outputs 4
Power Level / Signal Type
LVPECL, single ended (square wave)
SSB Phase Noise L(f) (dBc/Hz)
< 10 Hz
< 100 Hz
< 1 kHz
< 10 kHz
< 100 kHz
< 1 MHz
< 10MHz
Jitter, Integrated phase noise
< 200 fsec rms (10 Hz to 10 MHz)
Spurs
< -50 dBc, except harmonics
6 dB ref input change Will vary 1.8 dB output LO
0.3 x 6 = 1.8 dB
Square wave,
or Sine wave,
That is the question!!
LO output variations:
Due to ref input level (cable losses): constant
Due to ref input temp variations (±0.1dB)x0.3=0.06dB
Due to LO box temp variations: 0.05x4=0.2dB
REFERENCE INPUT
Frequency
MHz
Power Level range
2 dBm ± 3 dB (sine)
Power level variations
< ±0.1 dB
Return Loss
> 14 dB (50 ohm)
SSB Phase Noise L(f) (dBc/Hz)
< 10 Hz
< 100 Hz
< 1 kHz
< 10 kHz
< 100 kHz
< 1 MHz
< 10MHz
Jitter/Integrated phase noise
< 50 fsec rms (10 Hz to 1 MHz)
Harmonics
< -60 dBc
Spurious
< -80 dBc
Total variations due to temp.:
0.26 dB
REFERENCE OUTPUT
Frequency
MHz
Power Level
15 dBm ± 1 dB (sine)
Return Loss
14 dB (50 ohm)
Jitter degradation
Negligible (< 5 fsec rms added)
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

18. MONITORING AND CONTROL
LO Box Specs
MECHANICAL
RF/clock connectors
SMA(f), single-ended
Power Supply Connector
IEC
Monitoring Interface
ETHERNET (RJ45)
Interlock interface connector
Souriau UT00128SH or equivalent (TBC)
On/Off switch
Front panel
Dimensions
19” rack, 2U
MONITORING AND CONTROL
Front panel indicators (LEDs)
AC OK, DC OK, Ref in OK, Ref out OK, LO OK, CLK OK
Remote Interface
TCP/IP (the unit will be integrated in EPICS)
e.g.: using an XT-PICO-SXL from AK-Nord or similar
LO/CLK 1Frequency select
Ethernet, Input
REF Input monitoring
Ethernet, output
REF Output monitoring
CLK monitoring
LO monitoring
Power supply voltage
Power supply current
Internal temperature
Front panel LEDs
LO/CLK Frequency selection
Monitoring
In case Will be needed in future
ELECTRICAL
Supply Voltage
220 Vac, 50 Hz
Power Consumption
< 30 W
INTERLOCKS
Enable/Disable
0V/24V, 5mA max., Input (0V: Enable, 24V: Disable)
Ready/Fault
Dry contact (N.O.), Output (Closed: Ready, Open: Fault)
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

19. LO Splitter Box Specs One output Will be used for monitoring
LO specs of splitter box
Number of LO inputs 4
Number of LO outputs
16 (4 x 4)
Frequency range
370 – 390 MHz
Input power range
12 ± 1 dBm
Output power level
17 ± 1 dBm
Input / Output impedance
50 Ω
Input / Output return loss
> 14 dB
Jitter degradation
Negligible (< 5 fsec rms added)
Harmonics
< -50 dBc
Spurious
< -70 dBc
Amplitude unbalance
< 0.3 dB, peak to peak, between outputs
Phase unbalance
< 5 deg, peak to peak, between outputs
Gain variation due to temperature
< 0.01 dB/degC, over the operating temperature range
Clock signals of splitter box
Number of CLK inputs 4
Number of CLK outputs
16 (4 x 4)
Clock frequency range
MHz
Power Level / Signal Type
LVPECL, Single ended
Jitter degradation
Negligible (< 5 fsec rms added)
One output Will be used for monitoring
To be confirmed
To compensate probable losses between Spliter box and diferente LLRFs
MONITORING AND CONTROL
Front panel Indicators (LEDs)
AC OK, DC OK, LO OK, CLK OK
Remote Interface
TCP/IP (the unit will be integrated in EPICS)
XT-PICO-SXL from AK-Nord or similar
LO Input monitoring
Ethernet, output
LO Output monitoring
CLK Input monitoring
CLK Output monitoring
Power supply voltage
Power supply current
Internal temperature
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

20. MECHANICAL (Splitter box)
LO Splitter Box Specs
MECHANICAL (Splitter box)
RF/clock connectors
SMA(f), single-ended
Power Supply Connector
IEC
Monitoring Interface
ETHERNET (RJ45)
Interlock interface connector
Souriau UT00128SH or equivalent (TBC)
On/Off switch
Front panel
Dimensions
19” rack, 2U
INTERLOCK
Ready/Fault
Dry contact (N.O.), Output (Closed: Ready, Open: Fault)
Environmental
Value
Comments
Operation temperature
25 ± 5 degC
Critical performances only should be valid within ±2 degC
Storage temperature
0 – 50 degC
Operating humidity
<90%, non-condensing
EMC/EMI
TBD
CE marking
Yes
ELECTRICAL
Supply Voltage
220 Vac
Power Consumption
< 10 W
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LLRF CDR, ESS, Lund, January 2019

21. LLRF CDR, ESS, Lund, January 2019
QA & Risk Management
To help manufacturer and avoid delays, ESS-Bilbao procures some components with long lead time such as ceramic filters
ESS-Bilbao will provide a bill of materials used in prototype as a guidance for the industry partner and will transfer relevant experiences
Compliance with CE marking will be required. This can be done by “Declaration of Conformity”
Getting offers from industry partners and contracting should be done soon.
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

22. LLRF CDR, ESS, Lund, January 2019
Next steps
After this CDR, final technical specifications will be sent to potential suppliers to get their offers and proceed with the tender process.
For the clock generation should be decided to use LVPECL square signals or sinewave signals.
After finishing the fabrication, tests will be done as follows:
FAT for all units in manufacturer premises
SAT1 for one LO box at ESS-Bilbao in our buncher cavity test stand along with one LLRF unit
SAT2 for all LO units and the splitter box at ESS.
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019

23. LLRF CDR, ESS, Lund, January 2019
Thank you
A.Kaftoosian
LLRF CDR, ESS, Lund, January 2019