Presentation is loading. Please wait.

Presentation is loading. Please wait.

Cypress Roadmap: Asynchronous SRAMs

Published byWidyawati Gunawan Modified over 5 years ago

Similar presentations

Presentation on theme: "Cypress Roadmap: Asynchronous SRAMs"— Presentation transcript:

1 Cypress Roadmap: Asynchronous SRAMs
Q2 2015

2 Low-Power SRAM (MoBL®: More Battery Life)
Asynchronous SRAM Portfolio High Density | Wide Voltage Range | Automotive A, E1,2 | On-chip ECC3 Fast SRAM Low-Power SRAM (MoBL®: More Battery Life) PowerSnooze™4 Serial SRAM Non-ECC ECC3 Quad-SPI, ECC3 32Mb-128Mb Other Densities NDA Required Contact Sales CY6218x 64Mb; 2.5, 3.0 V 55 ns; x8, x16 Ind5 Other Densities NDA Required Contact Sales Other Densities NDA Required Contact Sales Other Densities NDA Required Contact Sales CY7C107x 32Mb; 3.3 V 12 ns; x8, x16 Ind5 CY6217x 32Mb; 2.5, 3.0, 5.0 V 55 ns; x8, x16 Ind5 CY7C106x 16Mb; 1.8, 3.3 V 10 ns; x8, x16, x32 Ind5 CY7C106x 16Mb; V 10 ns; x8, x16, x32 Ind5, Auto E2 Q215 CY6216x 16Mb;1.8, 3.0, 5.0 V 45 ns; x8, x16 Ind5, Auto A1 CY6216x 16Mb; V 45 ns; x8, x16, x32 Ind5, Auto E2 Q215 CY7S106x 16Mb; V 10 ns; x8, x16, x32 Ind5, Auto E2 Q215 CY7C105x 8Mb; 3.3 V 10 ns; x8, x16 Ind5 CY7C Mb; 3.3 V 10 ns; x24 Ind5 CY6215x 8Mb; 1.8, 3.0, 2.5-5V 45 ns; x8, x16 Ind5, Auto A1, E2 2Mb-16Mb CY7C104x 4Mb; 3.3, 5.0 V 10 ns; x4, x8, x16 Ind5, Auto A1, E2, RH6 CY7C Mb; 3.3 V 10 ns; x24 Ind5 CY7C104x 4Mb; V 10 ns; x8, x16 Ind5, Auto E2 Q315 CY6214x 4Mb; 1.8, 3.0, 2.5-5V 45 ns; x8, x16 Ind5, Auto A1, E2 CY6214x 4Mb; V 45 ns; x8, x16 Ind5, Auto E2 Q315 CY7S104x 4Mb; 3.3 V 10 ns; x8, x16 Ind5, Auto E2 Q315 CY7C1010/11 2Mb; 3.3 V 10 ns; x8, x16 Ind5, Auto A1, E2 CY7C1024 3Mb; 3.3 V 10 ns; x24 Ind5 CY6213x 2Mb; 1.8, V 45 ns; x8, x16 Ind5, Auto A1, E2 CY7C1020 512Kb; 2.6, 3.3, 5.0V 10 ns; x16 Ind5, Auto E2 CY7C1019/21/100x 1Mb; 2.6, 3.3, 5.0 V 10 ns; x4, x8, x16 Ind5, Auto A1, E22 CY6212x 1Mb; 1.8, V 45 ns; x8, x16 Ind5, Auto A1, E2 64Kb-1Mb CY7C185 64Kb; 5.0 V 15 ns; x8 Ind5 CY7C19x/ Kb; 3.3, 5.0 V 10 ns; x4, x8 Ind5, Auto A1 CY Kb; 5.0 V 55 ns, 70 ns; x8 Ind5 CY Kb; 1.8, 3.0, 5.0V 55 ns; x8 Ind5, Auto A1, E2 1 AEC-Q ºC to +85ºC 2 AEC-Q ºC to +125ºC 3 Error-correcting code 4 Fast SRAM with low-power sleep mode 5 Industrial grade -40ºC to +85ºC 6 Radiation hardened, military grade -55ºC to +125ºC Production Development QQYY Availability Sampling Concept Status

3 Fast SRAM with ECC Applications Family Table Features Block Diagram
Switches and routers IP phones Test equipment Automotive Computation servers Military and aerospace systems Density MPN Access Time Supply Current (Max. at 85ºC) 4 Mb CY7C104x 10 ns 45 mA 16 CY7C106x 110 Features Block Diagram Access time: 10 ns Multiple bus-width configurations: x8, x16 and x32 Wide operating voltage range: V Available in industrial and automotive temperature grades Industry-standard, RoHS-compliant packages Error-correcting code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error indication (ERR) pin to indicate single-bit errors Fast SRAM with ECC SRAM Array Address Decoder ECC Encoder Input Buffer x8, x16, x32 18-23 Data I/O Mux ERR Address SRAM Array Sense Amps ECC Decoder Control Logic CE OE WE BHE1 BLE2 Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Now (16Mb), Now (4Mb) Production: Q (16Mb), Q (4Mb) 1 Byte high enable 2 Byte low enable

4 Standby Current (Max. at 85ºC)
MoBL®3 SRAM with ECC Applications Family Table Programmable logic controllers Handheld devices Multifunction printers Automotive Implantable medical devices Computation servers Density MPN Standby Current (Max. at 85ºC) Standby Current (Typ. at 25ºC) 4 Mb CY6214x 8.7 µA 3.7 16 CY6216x 5.3 Features Block Diagram Standby current: 16 µA for 16Mb (see Family Table) Multiple bus-width configurations: x8, x16 and x32 Wide operating voltage range: V Available in industrial and automotive temperature grades Industry-standard, RoHS-compliant packages Error-correcting code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Error indication (ERR) pin to indicate single-bit errors MoBL®3 SRAM with ECC SRAM Array Address Decoder ECC Encoder Input Buffer x8, x16, x32 18-23 I/O Mux Data ERR Address SRAM Array Sense Amps ECC Decoder Control Logic CE OE WE BHE1 BLE2 Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Now (16Mb), Now (4Mb) Production: Q (16Mb), Q (4Mb) 1 Byte high enable 2 Byte low enable 3 More Battery Life

5 Fast SRAM With PowerSnooze™
Applications Family Table Programmable logic controllers Handheld devices Multifunction printers Automotive Computation servers Density MPN Access Time Deep Sleep Current (Max. at 85ºC) 4 Mb CY7S104x 10 ns 15 µA 16 CY7S106x 22 Features Block Diagram Access time: 10 ns or 12 ns (see Family Table) PowerSnooze™: Additional power-savings (deep-sleep) mode Deep-sleep current: 23 µA for 16Mb (see Family Table) Multiple bus-width configurations: x8, x16 and x32 Wide operating voltage range: V Available in industrial and automotive temperature grades Industry-standard, RoHS-compliant packages Error-correcting code (ECC) to detect/correct single-bit errors Bit-interleaving to avoid multi-bit errors Fast SRAM with PowerSnooze™ ECC Encoder Input Buffer Address Decoder Data x8, x16, x32 Address SRAM Array I/O Mux 20 ERR Power Management Block (Enables PowerSnooze) Sense Amps ECC Decoder Control Logic DS1 CE OE WE BHE2 BLE3 Collateral Availability Preliminary Datasheet: Contact Sales Sampling: Now (16Mb), Now (4Mb) Production: Q (16Mb), Q (4Mb) 1 Deep sleep 2 Byte high enable 3 Byte low enable

Download ppt "Cypress Roadmap: Asynchronous SRAMs"

Similar presentations

The Industry’s Smallest 16 Bit ADC’s

The Industry’s Smallest 16 Bit ADC’s
Computer Organization and Architecture

Computer Organization and Architecture
Memory Address Decoding

Memory Address Decoding
5-1 Memory System. Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable)

5-1 Memory System. Logical Memory Map. Each location size is one byte (Byte Addressable) Logical Memory Map. Each location size is one byte (Byte Addressable)
System Design Tricks for Low-Power Video Processing Jonah Probell, Director of Multimedia Solutions, ARC International.

System Design Tricks for Low-Power Video Processing Jonah Probell, Director of Multimedia Solutions, ARC International.
Flip-Flops.

Flip-Flops.
Memory Technology “Non-so-random” Access Technology:

Memory Technology “Non-so-random” Access Technology:
Section II Basic PLD Architecture. Section II Agenda  Basic PLD Architecture —XC9500 and XC4000 Hardware Architectures —Foundation and Alliance Series.

Section II Basic PLD Architecture. Section II Agenda  Basic PLD Architecture —XC9500 and XC4000 Hardware Architectures —Foundation and Alliance Series.
Cypress Roadmap: Trackpad Module

Cypress Roadmap: Trackpad Module
Typical Microcontroller Purposes

Typical Microcontroller Purposes
Cypress Roadmap: Automotive Products

Cypress Roadmap: Automotive Products
K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.

K.C.RAVINDRAN,GRAPES-3 EXPERIMENT,OOTY 1 Development of fast electronics for the GRAPES-3 experiment at Ooty K.C. RAVINDRAN On Behalf of GRAPES-3 Collaboration.
Owner : SAYD Cypress Confidential Sales Training 2/21/2013 1 FTDI FT232R vs. USB Serial CY7C65213 USB - UART Converter Cable USB to UART Conversion at.

Owner : SAYD Cypress Confidential Sales Training 2/21/ FTDI FT232R vs. USB Serial CY7C65213 USB - UART Converter Cable USB to UART Conversion at.
Sales Training 3/15/2013 Owner : JOCA Cypress Confidential TI UCD90160 vs. Cypress PSoC 3 Power Supervision Applications More Rails on a One-chip Solution.

Sales Training 3/15/2013 Owner : JOCA Cypress Confidential TI UCD90160 vs. Cypress PSoC 3 Power Supervision Applications More Rails on a One-chip Solution.
001-91017 Owner: TUP Rev *D Cypress Introduces the Industry’s Fastest High-Density NVRAM Solution 16Mb nvSRAM New Product Introduction 16Mb nvSRAM New.

Owner: TUP Rev *D Cypress Introduces the Industry’s Fastest High-Density NVRAM Solution 16Mb nvSRAM New Product Introduction 16Mb nvSRAM New.
001-96132Owner: SKRG Rev *A Tech lead: EWOO 1Mb Quad SPI nvSRAM Quick Presentation 1 Quick Presentation: 1Mb Quad SPI nvSRAM Eliminate Batteries and Reduce.

Owner: SKRG Rev *A Tech lead: EWOO 1Mb Quad SPI nvSRAM Quick Presentation 1 Quick Presentation: 1Mb Quad SPI nvSRAM Eliminate Batteries and Reduce.
Cypress Roadmap: Aerospace Memory

Cypress Roadmap: Aerospace Memory
001-91656Owner: NJX Rev ** Automotive Asynchronous SRAM Product Family Presentation Cypress Has the Industry’s Broadest Portfolio of High-Speed, Low-Power.

Owner: NJX Rev ** Automotive Asynchronous SRAM Product Family Presentation Cypress Has the Industry’s Broadest Portfolio of High-Speed, Low-Power.
001-95006Owner: JAYA Cypress Timing Solutions Roadmap Rev*BBUM: CNX Q1 2015 Cypress Roadmap: Timing Solutions.

Owner: JAYA Cypress Timing Solutions Roadmap Rev*BBUM: CNX Q Cypress Roadmap: Timing Solutions.
Cypress Confidential Owner: VBHU Sales Training 03/15/2013 Everspin MR4A16B vs. Cypress 16Mb NVSRAM High Frequency Parallel NVSRAM with Multiple Interface.

Cypress Confidential Owner: VBHU Sales Training 03/15/2013 Everspin MR4A16B vs. Cypress 16Mb NVSRAM High Frequency Parallel NVSRAM with Multiple Interface.

Similar presentations

Ads by Google