1. Welcome to the FPGA Tools Course Agenda

2. Class Objective At the end of this class, you will be able to:
Easily implement a design in an FPGA
Effectively use timing specifications
Easy creation of timing specifications
Efficient verification of design performance
Efficiently find more information after this class

3. Objectives Design Entry Options Implementation of FPGA Designs
Easy Ways to Improve Design Performance
Understand hardware and software options for fast and effecient FPGA designs
Online Documentation (Appendix)

4. Day 1 Outline Design Manager Design Entry
LogiBLOX GUI and the Core Generator
LogiBLOX and Design Manager Labs
Report Browser
Basic Timing Constraints
Timing Analyzer
Timing Optimization Lab
Implementation Options
Hardware Options
Online Documentation (Appendix)