1. Description and Analysis of MULTIPLIERS using LAVA

2. Today: Describe the most common multiplier circuits
In general
As Lava descriptions
Analyze them using Lava
Self optimizing descriptions
Time and size estimations

3. Lava advantages
Efficient description of very complex structured circuits
Automatically generic description (in contrast to e.g VHDL)
Efficient use of formal verification
Inheritance of the power of Haskell

4. Binary multiplication
All algorithms use the ”sum of partial products” method:
Possible trade-off:
Many PPs – Easier generation
Fewer PPs – Complex generation

5. Binary multiplication
Decomposition of the multiplier:

6. Binary multiplication
Partial product selection method:
Pi = Si  N (shifted to the same position as Si )
Example:

7. Binary multiplication
Two basic steps:
Generation of partial products (PPG)
Summation of partial products
Several methods exitst for each step
Famous: Booth, Wallace…
Goal:
To be able to combine any method for the first step with any method for the second step

8. Interface All PPs start from position 0 (shift by padding zeroes)
Use adders whose result has the same length as the longest input (no carry-out)
When carry-out is needed (only 1-bit selection), pad with one zero after

9. Simple PPG (1-bit selection)

10. Bit multiplier

11. Carry-propagate adder

13. Linear array summation

14. Adder tree summation

15. Simple multipliers

16. Booth’s algorithm (s-bit selection)
The number of PPs is m/s
s-1 adders are used in the selection

17. Improved Booth 2
Booth 2 selects part. prod. values from {0,N, 2N, 3N} BUT, 3N = 4N – N
So, instead of 3N, select –N
The next part. prod. selection has to compensate for this

18. New selection method

19. Improved Booth s The number of PPs is m/s+1 s-2 adders are used
The negation of PPs can easily be integrated into the selection procedure

21. Improved Booth s

22. The carry-save adder

23. The carry-save array

24. Speed up summation with faster adders (logarithmic)
Linear array has several equal-length critical paths  All adders need to be replaced
The carry-save array has only ONE critical path  Replace only the final CPA

25. Logarithmic adder (Ladner – Fisher)

26. Wallace tree

27. Wallace tree
Sums in O(log m) steps

28. Reducing hardware
All circuits have used lots of constant bits, which need unnecessary hardware
Circuits operating on constant bits can be reduced
Sufficient to make the reduction in the basic gates (inv, and, nand, or, nor, xor, xnor)
The reduction of the larger circuits follows automatically

29. Interpretations
Standard:
Symbolic:
Non-standard…

30. Self-reducing gates Constant bits: low, high
Everything else is variable
var ”a”
inv high

31. Reduction of larger circuits

32. Time estimation

33. Size estimation
Problem with sharing:

34. Redifinition of basic gates

35. Redefinition of AND

36. Estimation functions

37. Estimations

38. Results
Different selection group lengths with linearArray summation:

39. Results
Wallace summation instead:

40. Results
Different summation networks with simple PPG:

41. Results
Regular summation networks:
addTree carrySave

42. Limitations of the estimations
Wiring delays
Needs layout information
Fan-out
Several inputs connected to the same output  slower signal
Only standard gates are used
Better techniques exist for e.g full adders