1. Branch instructions Branch : B{<cond>} label
Branch with Link : BL{<cond>} subroutine_label
The branch offset must take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction
The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC
± 32 Mbyte range
How to perform longer branches?

2. ARM Branches and Subroutines
B <label>
PC relative. ±32 Mbyte range.
BL <subroutine>
Stores return address in LR
Returning implemented by restoring the PC from LR
For non-leaf functions, LR will have to be stacked

3. ARM subroutine linkage
Branch and link instruction:
BL foo
Copies current PC to r14.
To return from subroutine:
MOV r15,r14

4. ARM ADR pseudo-op
Cannot refer to an address directly in an instruction.
Generate value by performing arithmetic on PC.
ADR pseudo-op generates instruction required to calculate address:
ADR r1,FOO

5. Contd…

6. How ADR works?

7. Example: C assignments
x = (a + b) - c;
y = a*(b+c);
z = (a << 2) | (b & 15);
if (a > b) { x = 5; y = c + d; } else x = c - d;
Assembler: ???