1. Small Geometry Effects of MOSFETs
Geometry Effects on VTH L W VG VS VD n+ NA
It has been found experimentally that as L, W ¯, VTH becomes dependent on L, W and VD.

2. Threshold voltage changes due to short channel effects (SCE).
Threshold voltage changes due to narrow width effects (NWE).

3. Small geometry effects can be modeled using 2D or 3D computer simulators. However, simple analytic formulae for these effects are desirable, because such equations permit physical insight, and allow optimization of device design. Many papers have appeared in the literature attempting to analyze this problem. We will consider only the simplest approaches which represent the main ideas in many of these papers, namely “charge-sharing”.
(From Yau, Solid State Elec., p (1974) )

4. In a long channel device, charge conservation
Also
with

5. Assume only the charges inside the trapezoid is supported by the gate, i.e., the junctions support the remaining charges. This implies that QB is smaller than in a long channel device, and for a given VG, QI is larger to maintain neutrality.
The total charge in the trapezoid is :
Note

6. Straightforward trigonometric analysis then yields:
Assume that the non-uniform QB distribution can be averaged over L in its effect on VTH (this is a key assumption):
This is the desired result, which predicts VTH as a function of L, rj, and WD or NA for VD =0.

8. Theoretical curves of the threshold voltage as a function of channel length, for various junction depths.
Theoretical threshold voltage as a function of channel length for various substrate dopings.

9. Comparison of theory and experiment. T=297K, tox=Å, rj=0. 5mm, ND=1
Comparison of theory and experiment. T=297K, tox=Å, rj=0.5mm, ND=1.6X1016 cm-3, VFB=0.30 V.

10. The formulation by Yau’s model provides reasonable agreement with experiments, at least under some conditions. Other data bring into question the 1/L dependence, also; so far no VDS dependence has been included. In order to incorporate the influence of drain voltage on VTH, Taylor has modified Yau’s analysis, as follows:
Cross-sectional view of MOS device showing the division of charge between the source, gate, and drain electrodes for a short channel device (a) before the occurrence of punch-through, (b) after punch-through in the bulk has occurred.
IEEE TED, p. 337, March 1978

11. The main change here is that WD near the drain increases to reflect VD ¹0, and the region under the gate near the source/drain regions is now a junction charge, rather than a gate charge; i.e., L3 and L4 ¹0.
Assuming that the abrupt depletion approximately holds in regions I and III (important approximation), we obtain:
For VD=0, Vbi»YS at VTH, sinceYS =2|fB|, therefore, L2»L, which is Yau’s model described above.

12. For VD¹0, eqn. (8) may be used to show (see Taylor’s paper) that:
where
Terms associated with the source side offset (L3) have been neglected.
If we assume in this expression that VDS = 0 and Vbi=2|fB|, we see that above equation becomes the one from Yau’s model .

13. In the case of deep junction, i.e.
the equation simplifies to

14. Variation of threshold voltage with channel length in a short-channel MOSFET for various substrate and drain bias voltages. The parameters used were VFB=0.7V, ND=1.6X1016 cm-3, rj=0.5mm, and tox=500Å.
Variation of threshold voltage with oxide thickness and channel length and comparison with numerical solutions. The calculations were made for NA=5.6X1016cm-3, VFB=0V, rj=0.5mm, and tox=500Å.
The added complexity of the Taylor model does permit “reasonable” estimation of VD effects on VTH.

15. It is important to realize what these models imply about the potential at the Si/SiO2 interface (see figure below). For VD > 0, or for small L such that L4 is a significant fraction of L, the surface potential along the entire channel is reduced by VDS or Q’B(L4). This is a necessary consequence of the way these models are derived.

16. Now the depletion layer cannot abruptly change from WD to 0.
Narrow Width Effect
In addition to channel length effects on VTH, small channel widths also affect VTH QI QB W p- VG
Now the depletion layer cannot abruptly change from WD to 0.

17. More realistic field isolation schemes look like:VG QB p- QB W p+ p- VG
LOCOS with channel stop implants.
Fully recessed trench oxide
These structures further complicate the analysis. We will come back to this later.
First, consider the uniformly doped substrate with no channel stops and VD » 0 (Ref. Merchel, Solid State Elec., p. 1207, 1980).

18. QBW º triangular area charge under thick oxide, supported by the gate rj L N+ WD
QBW º triangular area charge under thick oxide, supported by the gate
QBL º trapezoidal area charge supported by gate (Yau)
a = parameter presumably dependent on oxide, thickness, doping, shape of oxide step, etc., which will most likely have to be experimentally determined.

19. The shape is rectangular on top, the sides are triangular and slope inward.
From Yau’s model

20. Simple geometry derivation gives:
Assume that the narrow width and the short channel effects can be simply superimposed, so that the total charge supported by the gate is given by:

21. Again assume that the QB can be average over the entire gate area, we have:
i.e.,
where

22. Note that if W® 0, this expression reduces Yau’s model
Note that if W® 0, this expression reduces Yau’s model. Note also that if L or W® ¥, the normal long channel VTH equation is obtained.
The parameter a is likely to be very different for different technologies, and is difficult to calculate since it depends on so many parameters.  

23. In any practical structure, oxide steps will be tapered, especially in LOCOS (locally oxidized) structures, further complicating calculation of a. a needs to be determined experimentally for a given process and set of design rules (or by computer simulation if the cross-section structure is known).
Practically

25. L > 3mm
L < 3mm
note that for the device T9 (L » 0.9mm on mask, L » 0.6mm in device), disagreements between experiment and theory are apparent.

26. Comparison of theory, experiment, and numerical calculations for narrow channels (W(mm) £ 10mm)
Comparison of theory and numerical calculations for narrow channels (1£ W(mm) £ 20)
For high resistivity substrates (12W cm) and ion-implanted channels, agreement is also reasonable. No field implant was used in the experimental devices. Again, a » 0.25.

27. L.C.D. = Large Geometry Device S.C.D. = Short channel device
N.W.D.= Narrow width device S.G.D.= Small Geometry Device

28. Short Channel Effects in the Subthreshold Region
Note that when L↓, two things happen:
VTH decreases for VDS ≈ 0
VTH decreases for VDS > 0 when compared to VDS ≈ 0 in short channel devices.
However, subthreshold ID-VDS characteristics also shifted in short channel devices.

29. Taylor’s model can also be applied to the subthreshold regime, i.e.
where

30. Note that the Taylor’s model gives reasonable agreement with experiment for a variety of VDS and Vsub values.
We see that:
VDS affects not only VTH, but also subthreshold currents.
Subthreshold slope S does not scale, and is approximately constant. Therefore, to maintain same Ioff, VTH cannot be scaled, as required in the ideal scaling laws.

31. Drain-Induced Barrier Lowering
Now, Taylor model predicts that, for fixed VG,
In reality, it is noticed that as L is submicron or below, the VG (with VDS > 4kT) that causes a fixed (ID(VDS))/(W/L) drops exponentially with L! This can be modeled by the effect called drain-induced barrier lowering. This is different from the charge-sharing model (which is quite good for VTH roll-off):

32. In the charge sharing model, Isubthreshold ↑ because Leff↓, and because VTH ( or the term) ↓.

33. In the drain-induced barrier lowering (DIBL) model (c. f
In the drain-induced barrier lowering (DIBL) model (c.f. Troutman, “VLSI Limitations from drain-induced barrier lowering”, IEEE TED ED-26, p. 461, 1979), the potential barrier between the source and channel is reduced by VDS and small L. Therefore, the current flow increases because the barrier ↓ (two-dimensional computer simulation).
In principle, we should be able to analytically calculate Df for a given VDS or DL, but such analytic models usually involve infinite series methods (c.f. J.R. Pfiester et al., IEEE TED, p. 333, 1985), and the interpretation is not straightforward.

34. N+
Sub p- S G D p+
N+-polysilicon
Note: if the surface region is implanted to shift VTH as is common done, the DIBL may occur beneath the surface, where the doping is lighter.
Therefore, a deep, higher dose boron implant is often used to prevent the drain potential from “punch-through” to the source.

35. For small VDS, the gate can be used to shut off the DIBL current; then it is a surface current
For larger VDS, the gate has no control of the channel; the DIBL current is below the surface.
Bulk DIBL is analogous to collector-emitter punchthrough in a BJT.

36. As would be expected, short channel devices suffer from DIBL to a much greater degree than long channel structures.
DIBL is minimized by
minimizing drain voltage in ICs
maintaining fairly high surface doping levels (however, this can result in higher VTH)
utilizing a deep p+ implant to prevent subsurface DIBL

37. Substrate Resistivity Selection
Even choosing a substrate resistivity can be complicated because there are good arguments for both high and low doping levels.
NA high
less DIBL
less DVTH with L, W, VDS
ideal scaling
NA Low
better subthreshold slopes
low junction C
VTH (long channel) ≈ independent of NA
better backgate bias sensitivity

38. So, how do we compromise?
Note first that for n+-poly or Al gate NMOS (i.e., fms ≈ 0.6V), VTH (long channel) ≈ 0 for doping ≤ 5x1014cm-3. Therefore ion implants can easily control VTH, independent of r.