1. ECE 352 Digital System Fundamentals
Complex FSMs
In this presentation, we will examine complex FSM design in further depth by looking at a more complicated example where we already have created the state diagram.

2. Example Complex FSM
This is a sequential circuit that performs a series of register operations
Transition conditions may be based on input signals or register values
Some outputs may be register outputs; some inputs may be buses
R  R Q  Q
D  D
/ R  R
Q  Q
Here is the example complex FSM. As you can see, this machine performs a number of different register transfers during its operation. To avoid making the diagram any more complicated than it needs to be, we often do not explicitly show the register transfer statements when registers hold their values.
Note that the diagram uses a mix of Mealy and Moore notation. The register operations will eventually be controlled by Mealy outputs of the control unit, whereas output V (for valid) is a Moore output.
Transition conditions can be based on input values, status information from the datapath registers, or a mix of both.
Circuit outputs can come from the control or the registers, and they may be single bit values or buses.
Mix of Mealy/Moore
In this type of diagram, we assume registers “hold” if no operation is given

3. Example Complex FSM DIVISION What does this do?
Counts the number of times it can subtract the InB from InA without going negative
Sets output V = 1 for one cycle when it is finished
So, what does this machine do? When the START signal is asserted, it loads register R from input InA, and register D from input InB. It also clears register Q. Then, it counts how many times it can subtract D from R before the value in R would go negative. After that, it asserts output V for a single clock cycle, then goes back to the INIT state where it waits for START to be asserted again.
So what does this process accomplish? It’s doing division by repeated subtraction. Now, let’s look at this state diagram in more detail.

4. Breaking Down a Problem
What are the circuit inputs?
InA and InB are vector inputs (multi-bit busses) that are the operands for the division
START is a scalar signal that tells the circuit to begin processing
First, let’s look at the inputs. START is a single bit input. The machine waits in the INIT state until START is asserted. InA and InB are multi-bit data inputs that supply the operands for the division.

5. Breaking Down a Problem
What are the circuit outputs?
The data outputs of registers R and Q are the results of the division:
Q: quotient
R: remainder
Now we’ll look at the outputs. The outputs of the machine include the contents of registers R and Q. When the machine is done subtracting, Q contains the count of subtractions, which is the quotient, and register R contains the remainder. The V output is used to indicate that the machine has completed the division operation, and registers Q and R contain the results.
V indicates if the operation is complete

6. Breaking Down a Problem
What are the registers and their capabilities?
Register D:
D  InB
Load
D  D
Hold
D  D
Don’t forget implied “hold” behavior…
So what capabilities do the registers need to have? To determine what each register requires, we examine the state diagram, looking for all operations on each register.
Let’s start with register D. The only operation shown on the diagram is a load, but don’t forget that it also is assumed to have hold capability everywhere an operation is not shown.
/ D  D

7. Breaking Down a Problem
What are the registers and their capabilities?
Register D:
D  InB
Load
D  D
Hold
Register R:
R  InA
Load
R  R – D
Subtract
R  R
Hold
For register R, we can see that it needs load capability, as well as the ability to subtract the contents of D from itself. And of course, it needs to have hold capability.
/ R  R

8. Breaking Down a Problem
What are the registers and their capabilities?
Register D:
D  InB
Load
D  D
Hold
Register R:
R  InA
Load
R  R – D
Subtract
R  R
Hold
For register Q, we need a synchronous clear input. We know that it’s a synchronous clear because it is shown on the state diagram. Q also needs increment capability, and the ability to hold.
Register Q:
/ Q  Q
Q  0
Sync. Clear
Q  Q + 1
Increment
Q  Q
Hold

9. Breaking Down a Problem
What are the registers and their capabilities?
Register D:
D  InB
Load
D  D
Hold
Register R:
R  InA
Load
R  R – D
Subtract
R  R
Hold
Now we have identified all of the required registers and their capabilities.
Register Q:
Q  0
Sync. Clear
Q  Q + 1
Increment
Q  Q
Hold

10. Breaking Down a Problem
What are the control signals?
Register D:
loadD
D  InB
Load 1
We are designing the entire circuit, so we can choose what happens if multiple register control inputs are 1
D  D
Hold
Register R:
loadR
subR
R  InA
Load 1
R  R – D
Subtract
R  R
Hold
Next, we determine a set of control signals for each register. In this case, we’ll use unencoded signals, with the assumption that each register will hold if not commanded to do an operation.
Register D only has load and hold capability, so we’ll name its control signal loadD. The register should load when the signal is asserted, and hold otherwise.
Register R will have two control signals, one for load and one for subtract. It should do the corresponding operation when a signal is asserted, and hold if neither is asserted. The register should never be simultaneously told to both load and subtract, so we specify that operation as undefined and can use it as a don’t-care situation in the register design.
Register Q will have also two control inputs for its operations and its behavior will also be undefined if multiple control inputs are asserted. 1
Undefined
Register Q:
clrQ
incQ
Q  0
Sync. Clear 1
Q  Q + 1
Increment
Q  Q
Hold 1
Undefined

11. Breaking Down a Problem
What status information does the control FSM need from the datapath?
Condition
Status Flag
(R – D) > 0?
RgtD
RltD
ReqD
(R – D) < 0?
(R – D) == 0?
Now we can look at what information the control unit will need from the datapath. Notice that the control unit never needs to know the actual values of the operands. Instead, it only needs to know whether the difference between R and D will be greater than, less than, or equal to zero. We give these status signals names that make it easy to tell what they represent.

12. Breaking Down a Problem
Datapath:
Register R with inputs InA, loadR and subR
Register D with inputs InB and loadD
Register Q with inputs clrQ and incQ
Subtractor (R – D) with outputs RgtD, RltD, ReqD
Circuit outputs Q and R
Control FSM:
Inputs RgtD, RltD, ReqD from the datapath
Input START (circuit input)
Outputs clrQ, loadR, loadD, incQ, subR
Circuit output V
Three states (INIT, SUB, DONE)
We can now break down the problem into separate specifications for the datapath and the control unit.
The datapath consists of the three registers and a subtractor to perform R – D and generate the three status signals. The datapath also provides the circuit outputs Q and R from the registers of the same name, which represent the quotient and remainder results of the division when output V is true.
The control unit is an FSM with three states. It receives as inputs the three datapath status signals, as well as the START circuit input. It has outputs to command the required register operations. It also produces the V circuit output. In a complex FSM, circuit outputs may come from the datapath, the control unit, or both.

13. Define the Interface Datapath and control need to communicate
Some datapath inputs are control outputs
Some control inputs are datapath outputs
Notice that the control unit never knows either of the operands… …or the result!
The control unit and datapath need information from each other. The connections between them are their interface. The control unit drives the register control signals, and the datapath status outputs are inputs to the control unit.

14. Next Steps
Design each component (datapath and control) based on the defined interface between them
Create registers that respond correctly to the defined control signals
Create an FSM that generates the needed control signal values at the needed times
Now that we have defined the interface, the design of the components is independent
We can design them in either order…
To complete the circuit, we need to design the datapath and the control unit. Once we’ve defined the interface between them, we can design them in any order.

15. Design the Datapath
Design the registers based on the specific behavior, control signals, and status outputs
Datapath
To design the datapath, we connect the register symbols as required, and then design the internal logic for each register.

16. Design the Control
Redraw the complex FSM in terms of the newly-defined interface between datapath and control
Replace register condition tests with datapath status outputs (which are inputs to the control FSM)
Replace register transfer operations with datapath control inputs (outputs of the control FSM)
To design the control unit, we redraw the state diagram and replace all register operations or comparisons with the corresponding control or status signal.

17. Design the Control
Replace register condition tests with datapath status outputs (inputs to the control FSM)
RgtD /
We start with the original complex state diagram, and replace each comparison with the corresponding status signal.
ReqD /
RltD /
Inputs: START
RgtD
RltD
ReqD
Outputs: V

18. Design the Control
Replace register transfer operations with datapath control inputs (outputs of the control FSM)
RgtD
RgtD /
clrQ
loadR
subR
loadD
incQ
Then we replace each register operation with the corresponding control signal. Now we have a standard state diagram, albeit one that uses a mix of Mealy and Moore notation.
ReqD /
ReqD
RltD
RltD /
subR
incQ
Inputs: START
Outputs: V
clrQ
loadR
loadD
subR
incQ

19. Design the Control
Create FSM logic using either minimum-FF or one-hot design method
(one-hot shown here)
= QDONE + START ·QINIT
DINIT
= START·QINIT + RgtD·QSUB
DSUB
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
= (RltD + ReqD)·QSUB
DDONE
clrQ = loadR = loadD =
START·QINIT
(RgtD + ReqD)·QSUB
subR = incQ =
Next we implement our redrawn state machine, which is the control unit for our complex FSM. Here we design it using the one-hot methodology, so we simply write down the logic based on the state diagram. Pause to examine these equations and verify that they model this state diagram.
= QDONE V

20. Design the Control
Notice that there really are only two datapath control signals (the others are redundant)!
= QDONE + START ·QINIT
DINIT
= START·QINIT + RgtD·QSUB
DSUB
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
= (RltD + ReqD)·QSUB
DDONE
clrQ = loadR = loadD =
START·QINIT
(RgtD + ReqD)·QSUB
subR = incQ =
Notice that some of the control unit’s outputs to the datapath are redundant, since they have the same logic. We really only need two, not five, distinct outputs from the control unit to control the datapath. We may decide, however, to keep them as separate outputs from the control unit to make it easier to modify the machine if it turns out we had an error. Also, by keeping them separate, the meaning of each output matches its name. Inside the FSM we would not duplicate the logic; we would connect the output of the AND gate producing clrR to the loadR and loadD pins as well, and likewise for subR and incQ. That’s what we’ll do in the remainder of this example, although we’ll only show clrQ and subR on the waveforms.
= QDONE V

21. Block Diagram Revisited
Once the datapath and control are created, they can be combined to form the complete circuit
Datapath
Once we have created both the datapath and the control, we connect them to create the complete machine.

22. How Does The Timing Work?
Until a reset, we do not know what state we are in!
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
Now, let’s examine how this machine works by looking at a waveform and comparing it to the simplified state diagram.
Until the machine is reset, it is not known what state it is in, since the power-up behavior of the flip-flops is unknown.

23. How Does The Timing Work?
A reset puts the FSM into the INIT state, but does not affect the datapath registers…
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
So the first thing we do is reset the machine, placing it in the INIT state. Notice that this does not affect the datapath registers, which do not have asynchronous inputs.

24. How Does The Timing Work?
The datapath registers have not yet updated in response to clrQ…
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
In the next clock cycle, START is asserted, so the next state is SUB and clrQ is asserted. However, that won’t affect the registers until the next active clock edge. Remember, registers are built out of flip-flops, so they can respond to synchronous inputs only at the active clock edges.

25. How Does The Timing Work?
Datapath registers update at the active clock edge based on control signal values just before the edge!
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
In the next clock cycle, we have entered the SUB state. R and D have been loaded with the operands, and the three status signals became valid, reflecting the values of R and D. Since R is currently greater than D, we will remain in state SUB.

26. How Does The Timing Work?
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
Next, R is updated to hold the result of subtracting D from R. Note that in this cycle, the input operands are changing in preparation for the next operation, but that has no effect on this operation.

27. How Does The Timing Work?
clrQ
RgtD /
loadR
subR
loadD
incQ
RltD /
ReqD /
subR
incQ
We continue subtracting until R is less than or equal to D.
Keep subtracting until R is less than or equal to D…

28. How Does The Timing Work?
ReqD /
subR
incQ
RgtD /
loadR
loadD
clrQ
RltD /
When that happens, the division operation is complete, so the next state becomes DONE and subR goes to zero to indicate that we should no longer update R with R – D.
Now R is less than D, so the division is complete…

29. How Does The Timing Work?
Assert V to indicate that the Q and R values are the (valid) final result
In the next clock cycle, the machine goes to the DONE state. In that state, the V output is asserted to indicate the operation is complete and the values in Q and R are now valid.

30. How Does The Timing Work?
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
After the operation completes, unconditionally transition back to the INIT state
From the DONE state, the machine unconditionally returns to the INIT state and waits to be told to do another operation.

31. How Does The Timing Work?
Begin a new operation…
If START is asserted when it returns to the INIT state, it will begin a new operation at the next clock edge.

32. How Does The Timing Work?
Begin a new operation…
Inputs: START
Outputs: V
loadR
loadD
clrQ
RltD
RltD /
RgtD
RgtD /
ReqD /
ReqD
subR
incQ
At that edge, it will load the new operands and transition to the SUB state.

33. How Does The Timing Work?
In this case, we are dividing 13 by 27, so the correct answer is simply 0 with a remainder of 13 and thus the machine will go to the DONE state at the next clock edge without performing a subtraction operation.
What happens here?

34. Analyzing the Complex FSM
What happens when InA < InB?
What happens when InA == InB?
What happens if InB == 0?
Does this work for signed numbers?
What is its max throughput (relative to fMAX)?
Pause here and take a few minutes to ponder these questions about the behavior of this complex FSM, and determine the answers based on the machine’s state diagram. The answers will be on the next slide, but you should be able to reason them out on your own.

35. Analyzing the Complex FSM
It goes directly from INIT to SUB to DONE, without doing a subtraction operation, so the answer will (correctly) be reported as 0 remainder InA.
It goes directly from INIT to SUB to DONE, doing a single subtraction operation so the answer will (correctly) be reported as 1 remainder 0.
If InA is not also equal to 0, the machine is stuck in state SUB forever! If InA is 0, it (incorrectly) reports the result as 1 remainder 0!
Not in general. It was designed for positive numbers, so it will not properly handle all combinations of positive and negative operands.
Max throughput is fMAX/3, since every division operation requires at least 3 clock cycles.
So, how did you do?

36. ECE 352 Digital System Fundamentals
Complex FSMs
Designing a complete system, with a control FSM and datapath registers, can be a complicated undertaking. This video looked at an example and how it could be broken down into a set of smaller problems to more easily understand and build it.