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pipelining: data hazards Prof. Eric Rotenberg
ECE 463/563 Fall `18 pipelining: data hazards Prof. Eric Rotenberg Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
Data Hazards read-after-write (RAW) hazard add r1, r2, r3 add r4, r1, r5 write-after-read (WAR) hazard add r2, r4, r5 write-after-write (WAW) hazard add r1, r4, r5 Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
RAW Hazard value needed value available value written IF add r1,r2,r3 ID IF add r4,r1,r5 EX ID IF MEM ID IF WB ID IF ID IF EX ID MEM EX WB MEM Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Data forwarding (bypasses)
IF/ID ID/EX EX/MEM MEM/WB RF NPC MUX D$ A ALU B MUX MUX IMM Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Data forwarding (bypasses)
IF/ID ID/EX EX/MEM MEM/WB RF NPC MUX D$ A ALU B MUX MUX IMM preliminary: moved this mux to prior stage Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Data forwarding (bypasses)
IF/ID ID/EX EX/MEM MEM/WB bypass 2 RF bypass 1 NPC MUX MUX D$ A ALU B MUX MUX MUX IMM Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Data forwarding (cont.)
EX ID IF add r6,r1,r5 byp 1 WB MEM EX ID IF add r8,r1,r5 byp 3 MEM EX ID IF add r7,r1,r5 byp 2 IF add r1,r2,r3 ID IF add r4,r1,r5 WB MEM EX ID WB MEM EX WB MEM WB Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Stalls due to RAW hazards
With bypasses No stall if producer is ALU type instruction Unavoidable 1-cycle stall if producer is a load instruction (cache hit) AND its dependent instruction is right behind it. This is because the dependent instruction must wait for BYPASS 2 for the load value. Note: If an instruction takes multiple cycles in EX (e.g., complex ALU operation) or multiple cycles in MEM (load/store cache miss), all instructions behind the long-latency instruction stall whether or not they depend on the data. The stall is attributable to a structural hazard caused by the current pipeline design (EX and MEM stages are “blocking” for multi-cycle instructions). EX ID IF value needed MEM ID IF value available byp 2 ID IF add r4,r1,r5 IF lw r1,#0(r2) WB EX ID MEM EX WB MEM Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
WAR and WAW Hazards WAR hazard A: ADD R1, R2, R3 B: ADD R2, R4, R5 Problem if B writes R2 before A reads R2 A will get the wrong value of R2 (that of B) Doesn’t happen in most in-order pipelines (like ours) Happens in out-of-order pipelines A may be stalled and B may be ready to execute out-of-order and write R2 WAW hazard B: ADD R1, R4, R5 Problem if B writes R1 before A writes R1 Later instructions will get the wrong value of R1 (that of A) A may be stalled and B may be ready to execute out-of-order and write R1 first Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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WAR and WAW Hazards (cont.)
Options for handling WAR and WAW hazards Stall the later instruction to defer its register write, OR Register renaming (see next major topic: ILP) Either way, compiler can limit the occurrence of WAR and WAW hazards by limiting the reuse of destination register specifiers among nearby instructions Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Types of program dependencies
True dependence (pure dependence, flow dependence) ADD R1, R2, R3 ADD R4, R1, R5 Causes RAW hazard if the two instructions are in the pipeline concurrently Anti-dependence ADD R2, R4, R5 Causes WAR hazard if the two instructions are in the pipeline concurrently Output dependence ADD R1, R4, R5 Causes WAW hazard if the two instructions are in the pipeline concurrently Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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Program dependencies (cont.)
A true dependence is called that, because there is truly a data dependency between the two instructions Producer-consumer relationship Second instruction needs the data produced by the first Anti-dependence and output dependence are sometimes clubbed together as false dependence because there isn’t actually a data dependency between the two instructions, just a register conflict Fall 2018 ECE 463/563, Microprocessor Architecture, Prof. Eric Rotenberg
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