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Aravindh Anantaraman*, Kiran Seth†, Eric Rotenberg*, Frank Mueller‡

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1 Aravindh Anantaraman*, Kiran Seth†, Eric Rotenberg*, Frank Mueller‡
Enforcing Safety of Real-Time Schedules on Contemporary Processors using a Virtual Simple Architecture (VISA) Aravindh Anantaraman*, Kiran Seth†, Eric Rotenberg*, Frank Mueller‡ Center for Embedded Systems Research (CESR) *Electrical & Computer Eng./ ‡ Computer Science North Carolina State University † Qualcomm. Inc Anantaraman © 2004 RTSS–25

2 Complexity in Hard-Real-Time Systems
Worst-case execution time (WCET) crucial for schedulability analysis Contemporary processors are extremely complex Branch prediction, pipelining, out-of-order execution Improve average case performance WCET unknown Complex processors not used in real-time systems Anantaraman © 2004 RTSS–25

3 Virtual Simple Architecture (VISA)
Simple Processor Anantaraman © 2004 RTSS–25

4 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Simple Processor Anantaraman © 2004 RTSS–25

5 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Simple Processor Complex Processor Anantaraman © 2004 RTSS–25

6 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = ?? (unreliable) Simple Processor Complex Processor Anantaraman © 2004 RTSS–25

7 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Simple Processor Complex Processor Anantaraman © 2004 RTSS–25

8 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Anantaraman © 2004 RTSS–25

9 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Anantaraman © 2004 RTSS–25

10 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Novel non-literal approach to static timing analysis Use simple processor as proxy for complex processor Dynamically guarantee WCET Anantaraman © 2004 RTSS–25

11 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems Anantaraman © 2004 RTSS–25

12 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization 100% processor utilization Anantaraman © 2004 RTSS–25

13 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization 100% processor utilization worst case worst case Anantaraman © 2004 RTSS–25

14 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization actual exec. time = 8 ms actual case 100% processor utilization worst case worst case Anantaraman © 2004 RTSS–25

15 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization actual exec. time = 8 ms actual case 100% processor utilization worst case dynamic slack worst case Anantaraman © 2004 RTSS–25

16 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization actual exec. time = 8 ms actual case actual case actual exec. time = 3 ms 100% processor utilization worst case dynamic slack worst case Anantaraman © 2004 RTSS–25

17 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization actual exec. time = 8 ms actual case actual case actual exec. time = 3 ms 100% processor utilization worst case dynamic slack worst case dynamic slack Anantaraman © 2004 RTSS–25

18 Virtual Simple Architecture (VISA)
Task X WCET = 10 ms Task X WCET = 10 ms Virtual Simple Architecture: give illusion of simple processor Simple Processor Complex Processor Worst-case equivalent systems 100% processor utilization actual exec. time = 8 ms actual case actual case actual exec. time = 3 ms 100% processor utilization worst case dynamic slack worst case dynamic slack Exploit dynamic slack for power/energy savings, other functionality Anantaraman © 2004 RTSS–25

19 Previous Approaches Avoid complexity
VISA allows complex processors to be used Disable complexity during hard-real-time tasks VISA disables complexity only when problematic Continue research in timing analysis WCET of simple proxy improved Anantaraman © 2004 RTSS–25

20 VISA Overview Provides real-time guarantees for contemporary processors Approach Execute tasks optimistically on complex mode Gauge interim progress Safe back-up mode for anomalous scenarios Anantaraman © 2004 RTSS–25

21 Dual-Mode VISA Processor
Static prediction Dynamic branch predictor Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Anantaraman © 2004 RTSS–25

22 Dual-Mode VISA Processor
Static prediction Dynamic branch predictor Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Anantaraman © 2004 RTSS–25

23 Dual-Mode VISA Processor
Static prediction Dynamic branch predictor Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Anantaraman © 2004 RTSS–25

24 Dual-Mode VISA Processor
Static prediction Dynamic branch predictor Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Anantaraman © 2004 RTSS–25

25 Dual-Mode VISA Processor
Static prediction Dynamic branch predictor Complex mode dynamic branch prediction superscalar out-of-order execution Simple mode static branch prediction scalar in-order execution Anantaraman © 2004 RTSS–25

26 VISA in Action simple mode Anantaraman © 2004 RTSS–25

27 VISA in Action simple mode complex mode Anantaraman © 2004 RTSS–25

28 VISA in Action Non-speculative simple mode simple mode complex mode
WCEC Non-speculative simple mode Anantaraman © 2004 RTSS–25

29 VISA in Action Non-speculative simple mode simple mode complex mode
WCEC 1 Non-speculative simple mode Anantaraman © 2004 RTSS–25

30 VISA in Action Non-speculative simple mode simple mode complex mode
WCEC 1 Non-speculative simple mode 2 Anantaraman © 2004 RTSS–25

31 VISA in Action Non-speculative simple mode simple mode complex mode
WCEC 1 Non-speculative simple mode 2 3 Anantaraman © 2004 RTSS–25

32 VISA in Action Non-speculative simple mode simple mode complex mode
WCEC 1 Non-speculative simple mode 2 3 4 Anantaraman © 2004 RTSS–25

33 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC’ Successful speculation in complex mode Anantaraman © 2004 RTSS–25

34 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode Anantaraman © 2004 RTSS–25

35 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode headstart Anantaraman © 2004 RTSS–25

36 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode 1 1 Anantaraman © 2004 RTSS–25

37 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode 1 1 2 Anantaraman © 2004 RTSS–25

38 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode 1 1 2 3 Anantaraman © 2004 RTSS–25

39 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode 1 1 2 3 4 Anantaraman © 2004 RTSS–25

40 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 chk3 chk4 WCEC’ Successful speculation in complex mode 1 1 2 3 4 $$$ cash back! dynamic slack Anantaraman © 2004 RTSS–25

41 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC’ Misspeculation in complex mode Anantaraman © 2004 RTSS–25

42 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 WCEC’ 1 1 Misspeculation in complex mode Anantaraman © 2004 RTSS–25

43 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 WCEC’ 1 1 (2) Misspeculation in complex mode Anantaraman © 2004 RTSS–25

44 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 WCEC’ 1 1 (2) 2 Misspeculation in complex mode Anantaraman © 2004 RTSS–25

45 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 WCEC’ 1 1 (2) 2 Misspeculation in complex mode 3 Anantaraman © 2004 RTSS–25

46 VISA in Action Non-speculative simple mode
complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 WCEC’ 1 1 (2) 2 Misspeculation in complex mode 3 4 Anantaraman © 2004 RTSS–25

47 WCET preserved in spite of missed checkpoint
VISA in Action simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk1 chk2 WCEC’ 1 1 (2) 2 Misspeculation in complex mode 3 4 WCET preserved in spite of missed checkpoint Anantaraman © 2004 RTSS–25

48 Contributions Minimize headstart overhead
Novel zero-overhead VISA approach – dynamic headstart accrual Extend VISA to multi-tasking systems Energy evaluation in multi-tasking systems Anantaraman © 2004 RTSS–25

49 Headstart Assessment simple mode complex mode Anantaraman © 2004
RTSS–25

50 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 Anantaraman © 2004 RTSS–25

51 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 Anantaraman © 2004 RTSS–25

52 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 Anantaraman © 2004 RTSS–25

53 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 chk1 chk2 chk3 chk4 headstart3 PEC1 PEC2 PEC3 WCEC3 WCEC4 Anantaraman © 2004 RTSS–25

54 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 chk1 chk2 chk3 chk4 headstart3 PEC1 PEC2 PEC3 WCEC3 WCEC4 Anantaraman © 2004 RTSS–25

55 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 chk1 chk2 chk3 chk4 headstart3 PEC1 PEC2 PEC3 WCEC3 WCEC4 Anantaraman © 2004 RTSS–25

56 Headstart Assessment simple mode complex mode chk1 chk2 chk3 chk4
WCEC3 WCEC4 WCEC2 WCEC1 PEC1 chk1 chk2 chk3 chk4 headstart3 PEC1 PEC2 PEC3 WCEC3 WCEC4 Anantaraman © 2004 RTSS–25

57 Explicit Padding Approach
Pad task WCEC with max headstart amount Give padded WCEC to schedulability analysis Anantaraman © 2004 RTSS–25

58 Dynamic Headstart Accrual
Harness naturally occurring dynamic slack in simple mode as headstart  switch to complex mode Anantaraman © 2004 RTSS–25

59 Dynamic Headstart Accrual
simple mode complex mode Anantaraman © 2004 RTSS–25

60 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 Anantaraman © 2004 RTSS–25

61 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Successful speculation in complex mode Anantaraman © 2004 RTSS–25

62 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Successful speculation in complex mode 1 Anantaraman © 2004 RTSS–25

63 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Successful speculation in complex mode 1 accrued slack > max (headstart2,3,4) ? NO Anantaraman © 2004 RTSS–25

64 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Successful speculation in complex mode 1 2 Anantaraman © 2004 RTSS–25

65 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Successful speculation in complex mode 1 2 accrued slack > max (headstart3,4) ? YES Anantaraman © 2004 RTSS–25

66 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC Successful speculation in complex mode 1 2 3 Anantaraman © 2004 RTSS–25

67 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 chk4 WCEC Successful speculation in complex mode 1 2 3 4 Anantaraman © 2004 RTSS–25

68 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 chk4 WCEC Successful speculation in complex mode 1 2 3 4 dynamic slack Anantaraman © 2004 RTSS–25

69 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 chk4 WCEC Successful speculation in complex mode 1 2 3 4 First simple mode, then complex mode No explicit headstart padding Anantaraman © 2004 RTSS–25

70 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Misspeculation in complex mode Anantaraman © 2004 RTSS–25

71 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC 1 Misspeculation in complex mode Anantaraman © 2004 RTSS–25

72 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC 1 Misspeculation in complex mode 2 Anantaraman © 2004 RTSS–25

73 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC 1 Misspeculation in complex mode 2 (3) Anantaraman © 2004 RTSS–25

74 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC 1 Misspeculation in complex mode 2 (3) 3 Anantaraman © 2004 RTSS–25

75 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC 1 Misspeculation in complex mode 2 (3) 3 4 Anantaraman © 2004 RTSS–25

76 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC Flexible: fluidly switch between simple and complex Anantaraman © 2004 RTSS–25

77 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC 1 Flexible: fluidly switch between simple and complex Anantaraman © 2004 RTSS–25

78 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC 1 Flexible: fluidly switch between simple and complex 2 Anantaraman © 2004 RTSS–25

79 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 WCEC 1 Flexible: fluidly switch between simple and complex 2 accrued slack > max (headstart3,4) ? YES Anantaraman © 2004 RTSS–25

80 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC 1 Flexible: fluidly switch between simple and complex 2 (3) Anantaraman © 2004 RTSS–25

81 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC 1 Flexible: fluidly switch between simple and complex 2 (3) 3 Anantaraman © 2004 RTSS–25

82 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 WCEC 1 Flexible: fluidly switch between simple and complex 2 (3) 3 accrued slack > headstart4 ? YES Anantaraman © 2004 RTSS–25

83 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 chk4 WCEC 1 Flexible: fluidly switch between simple and complex 2 (3) 3 4 Anantaraman © 2004 RTSS–25

84 Dynamic Headstart Accrual
simple mode complex mode WCEC 1 Non-speculative simple mode 2 3 4 chk3 chk4 WCEC 1 Flexible: fluidly switch between simple and complex 2 (3) 3 4 Re-enable speculation after missed checkpoint Anantaraman © 2004 RTSS–25

85 Explicit Padding vs. Dynamic Headstart Accrual
+Guaranteed speculation Inflated WCETs  Unschedulable task-sets Dynamic headstart accrual +Schedulability unaffected +Flexible switching Dependent on dynamic slack in simple mode Anantaraman © 2004 RTSS–25

86 VISA in Multi-Tasking Systems
Gauging mechanism (watchdog counter) disrupted Adapt for multi-tasking Interruption  save watchdog counter Resumption  restore watchdog counter Anantaraman © 2004 RTSS–25

87 Easy Integration in Multi-Tasking Systems
System software components depend on WCET EDF scheduler, DVS scheduler, etc. VISA preserves WCET abstraction We demonstrate VISA in a hard-real-time system with Look-Ahead EDF-DVS [Pillai&Shin’01] Anantaraman © 2004 RTSS–25

88 Look-Ahead EDF-DVS in VISA
Simple processor VISA (Explicit padding) VISA (Dynamic headstart accrual) Anantaraman © 2004 RTSS–25

89 Experimental Methodology
Cycle-accurate microarchitecture simulator Wattch power models to measure power/energy [Brooks00] 6 C-lab real-time benchmarks Anantaraman © 2004 RTSS–25

90 Energy Savings Anantaraman © 2004 RTSS–25
Energy savings across all taksets ranging from 24% to 58% Dynamic headstart accrual has more power savings since WCETs are unpadded – so lower frequencies are achieved Pipeline is reconfigured into complex mode in the beginning of the first task of simulation. Anantaraman © 2004 RTSS–25

91 Average Frequencies Anantaraman © 2004 RTSS–25
The frequencies for the VISA models is considerably lower than that of explicitly safe-simple The tasksets with the largest difference in frequencies yields the largest energy savings Dynamic headstart accrual has slightly lower frequencies than explicit padding Anantaraman © 2004 RTSS–25

92 High Utilization Task-sets
Worst-case utilization (unpadded WCETs) = 1.0 Cannot use explicit padding  task-set unschedulable Dynamic headstart accrual works! Anantaraman © 2004 RTSS–25

93 Energy Savings (U = 1) Anantaraman © 2004 RTSS–25
Utilization of 1.0 using unpadded WCETs -- explicit padding cannot be used Fine grained and coarse grained sub-tasks – headstart amount depends on sub-task sizes Fine grained has better performance than coarse grained – more wcets can be finished Anantaraman © 2004 RTSS–25

94 Coarse-grained vs. fine-grained sub-tasks
Coarse-grained sub-tasks 1 2 3 4 Fine-grained sub-tasks 1 2 3 4 5 6 7 8 Anantaraman © 2004 RTSS–25

95 Fine-grained vs. coarse-grained sub-tasks
Utilization of 1.0 using unpadded WCETs -- explicit padding cannot be used Fine grained and coarse grained sub-tasks – headstart amount depends on sub-task sizes Fine grained has better performance than coarse grained – more wcets can be finished Anantaraman © 2004 RTSS–25

96 Summary VISA enables use of complex processors in safe real-time systems Headstart calculation Novel zero-overhead VISA speculation technique dynamic headstart accrual VISA extended to multi-tasking systems 19% – 58% energy savings with respect to explicitly-safe simple processor Anantaraman © 2004 RTSS–25

97 Questions? Anantaraman © 2004 RTSS–25

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