1. Good Design & Network Audio
EECS150 Fall Lab Lecture #6
Chris Fletcher
Adopted from slides designed by
Greg Gibeling and Chris Fletcher
10/3/2008
EECS150 Lab Lecture #6

2. Today (1) Good Design Administrative Info FSMs: The Good, Bad and Ugly
Interfaces (Part 1)
Signal Conditioning
Administrative Info
10/3/2008
EECS150 Lab Lecture #6

3. Today (2) Lab #6: Network Audio Motivation Network Organization
Ethernet Packets
Eth2Audio
Async FIFO
10/3/2008
EECS150 Lab Lecture #6

4. Finite State Machines (1)
After all we have told you…
FSMs seldom lead to efficient circuits
The Real Story
When they are not useful
When they are useful
How you can tell between the two cases
10/3/2008
EECS150 Lab Lecture #6

5. Finite State Machines (2)
Most FSMs look like…
Important properties
Straight path
No complicated branching logic
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EECS150 Lab Lecture #6

6. Finite State Machines (3)
It’s a ring counter!
Bubble-Arc diagrams don’t necessitate the FSM design pattern
10/3/2008
EECS150 Lab Lecture #6

7. Finite State Machines (4)
Conclusion
Think simple
A counter is an incredibly powerful circuit
On the other hand…
Some FSMs look like…
(await the very necessary page turn)
10/3/2008
EECS150 Lab Lecture #6

8. Look any different? Complex branching! 10/3/2008
EECS150 Lab Lecture #6

9. Finite State Machines (6)
Do not use FSMs when you have…
Few branches
Linear transitions
Use FSMs when you have…
Many branches
Complicated decision logic
Conditional transitions
10/3/2008
EECS150 Lab Lecture #6

10. Signal Conditioning (1)
Off-by-a-cycle Errors
Shorten a Pulse
Lengthen a Pulse
Shift a Pulse
Adaptors between complex modules
Simple modification outside module
Don’t/Can’t touch module internally
10/3/2008
EECS150 Lab Lecture #6

11. Signal Conditioning (2)
Shorten a Pulse
5 Cycles -> 4 Cycles
Any guesses?
What if we delayed the input?
10/3/2008
EECS150 Lab Lecture #6

12. Signal Conditioning (3)
Shorten a Pulse
Out = In & In_Delayed
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EECS150 Lab Lecture #6

13. Signal Conditioning (4)
Lengthen a Pulse
Out = In | In_Delayed
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EECS150 Lab Lecture #6

14. Administrative Info Project starts next friday: 10/10 SVN Repositories
Digital Oscilloscope!
Commit to your partner
The first checkpoint is 1 week long
SVN Repositories
Will be online at the end of next week
Version-control tutorial on the way
10/3/2008
EECS150 Lab Lecture #6

15. Lab #6: Network Audio Play Audio off Ethernet
Receive Ethernet packets
Decode and remove header
Filter packets
Play audio data payload
A Major Project by Itself
Given: Ethernet, Audio, ETC
To be written: Packet Decode & Filtering
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EECS150 Lab Lecture #6

16. Lab #6: Network Audio Your project and Lab 6
Audio  Ethernet  Waveform
Stream audio into oscilloscope
Audio Visualizations
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EECS150 Lab Lecture #6

17. Network Organization (1)
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EECS150 Lab Lecture #6

18. Network Organization (2)
DO NOT MODIFY THE PRODUCTION NETWORK
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EECS150 Lab Lecture #6

19. Ethernet Packets (1) We’re using raw Ethernet Raw Ethernet:
No TCP/IP, its too complex
Cant use this on the internet
Raw Ethernet:
48bit Destination MAC Address
48bit Source MAC Address
16bit Ethernet Type
Payload
32bit CRC
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EECS150 Lab Lecture #6

20. Ethernet Packets (2)
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EECS150 Lab Lecture #6

21. Ethernet Packets (3) A Good Packet Total: 1028x 32bit Words
48bit Destination (0xFFFFFFFFFFFF)
48bit Source (0x0090c2001c50)
16bit Packet Type (0x0101)
16bit Padding (0x????)
1024x 32bit PCM Audio Data
10/3/2008
EECS150 Lab Lecture #6

22. Ethernet Packets (4) A Bad Packet Coping with bad packets
Who knows how long?
Source and Destination could be anything
Packet Type probably not 0x0101
Coping with bad packets
Do NOT send them to AudioTop
Just keep dropping data until end of packet
Done Signal: InPacketValid & InPacketInvalid
10/3/2008
EECS150 Lab Lecture #6

23. Lab #6: Eth2Audio (1)
10/3/2008
EECS150 Lab Lecture #6

24. Lab #6: Eth2Audio (2) Signal Width Dir Description DIn 32 I
Data from MAC_Top
InValid 1
Indicates DIn is valid
InPacketValid
Indicates the end of a good(crc) packet
InPacketInvalid
Indicates the end of a bad(crc) packet
EthernetClock
25MHz Ethernet Clock
EthernetReset
EthernetClock sync. Reset
AudioClock
12.288MHz Audio Clock
AudioReset
AudioClock sync. Reset
DOut O
Data out to AudioTop
OutRequest
AudioTop requesting a new word
OutValid
Indicates DOut is valid
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EECS150 Lab Lecture #6

25. Lab #6: Async FIFO (3) Buffer to match two data rates
Great for data path clock domain crossings
Write on one clock (WR_)
Read on another (RD_)
Good place to buffer audio
10/3/2008
EECS150 Lab Lecture #6

26. Lab #6: Eth2Audio (4) Design No FSMs allowed Word Counter
How many bits wide?
Valid Register
Stores whether the packet is valid or not
Reset
When do you reset word counter and valid register?
10/3/2008
EECS150 Lab Lecture #6

27. Lab #6: Eth2Audio (5) Testing Checkoff
We give you a very nice testbench
Read Lab5Testbench.v
Read Lab5TestPackets.txt
Fix your module in simulation
You can use ChipScope w/ 1 clock
Checkoff
We should hear nice clean audio
Show us your module using ChipScope
10/3/2008
EECS150 Lab Lecture #6