1. Welcome to Computer Architecture
Kevin Skadron

2. What is Computer Architecture?

5. Talk about Power Hungry…

6. Hot Chips are No Longer Cool!
Sun's
Surface
1000
Rocket
Nozzle
Nuclear Reactor
100
Watts/cm 2
Pentium® 4
Hot plate
Pentium® III
Pentium® II 10
Pentium® Pro
Pentium®
i386
i486 1
1.5m 1m
0.7m
0.5m
0.35m
0.25m
0.18m
0.13m
0.1m
0.07m
* “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” – Fred Pollack, Intel Corp. Micro32 conference key note

7. Ouch
Operating temperatures > 100°!

8. Graphics Cards Nvidia GeForce 5900 card, a.k.a. the “Dustbuster”
Source: Tech-Report.com

9. Prognostications Linear extrapolation: 2012, Pentium 8
12GHz, 8-way CMP, 4-way MT, 100MB L4 cache on die, 20GB/s optical I/O, 250W, 2TB hard drive
What will users do with this?
Sequential prophecy alternative A
What they do now. Somewhat faster. Commoditized.
Sequential prophecy alternative B
They won’t want them. They’ll want affordable, mobile, ubiquitous, secure computing based on huge local non-volatile storage with auto-backup
Comp Arch must anticipate both alternatives!
Courtesy of Bob Colwell

10. Physically-Aware
Architecture

11. ITRS Projections Zero-Sum Architecture?
2001 – was 0.4
These are targets, doubtful that they are feasible
Growth in power density means cooling costs continue to grow
High-performance designs seem to be shifting away from clock frequency toward # cores
Supply voltage scaling seems to be stopping
ITRS 2004
2001 – was 288

12. A New Era of Multi-Core Architectures
vs.
Source: Chrostopher Reeve Homepage,
Cores may also be heterogeneous, with a few powerful cores and very many small cores

13. Gate L variation due to Optical
High freq, high leakage
Low freq, low leakage
Note random var’s

14. Impact of Static Variations
1.4
Frequency
~30%
Leakage
Power
~5-10X
1.3
30%
1.2
130nm
Normalized Frequency
1.1
1.0 5X
0.9 1 2 3 4 5
Normalized Leakage (Isb)
Source: Shekhar Borkar, keynote presentation, MICRO-37, 2004

15. Sources, types of variations
Device variations
L (systematic)
Tox, Nd, W (random)
Interconnect
Width, thickness, height, crosstalk (mostly random)
Environmental
T, Vdd (heavy arch. dependence)
Package variations
TIM thickness, chip roughness, etc. (random)
Device variations
Primarily affect Vth
Vth
Leakage, frequency
Leakage  T
Temperature
Leakage, frequency, Vdd
Vcc
Package variations
Within-die T effects
Chip to chip too

16. Some Architecture Implications
Core-to-core variation: 10-30% freq.
Limitations on # cores, placement
Symmetry is expensive
Leakage increases by % if you Vth-compensate all cores to nominal
This would exacerbate thermal limitations, and probably require voltage scaling or throttling
Or you compensate all cores to slowest core, and leave performance on the table
SRAM variations will also lead to non-uniform caches

17. Classic
Equations

18. Important Performance Eqns.
CPU performance equation: insts cycles time
CPU time = prog inst cycle
Speedup = told / tnew
Amdahl’s Law:
Speedup = (1 – Fracenh) + Fracenh/Speedupenh

19. Implications of Amdahl’s Law

20. An Unbalanced System
CPU
I/O, Memory, Cache
Courtesy of Bob Colwell

21. Important Performance Eqns.
CPU performance equation: insts cycles time
CPU time = prog inst cycle
Speedup = told / tnew
Amdahl’s Law:
Speedup = (1 – Fracenh) + Fracenh/Speedupenh

22. Amdahl’s Law example