ECE 448 Lecture 4 Modeling of Circuits with a Regular Structure Constants, Aliases, Packages ECE 448 – FPGA and ASIC Design with VHDL.

ECE 448 Lecture 4 Modeling of Circuits with a Regular Structure Constants, Aliases, Packages ECE 448 – FPGA and ASIC Design with VHDL

Reading Required Recommended P. Chu, FPGA Prototyping by VHDL Examples
Chapter 3.6, Constants and Generics Recommended S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 6.6.4, Generate Statements Chapter A.7.5, Generate Statement Chapter A.10.9, Using Subcircuits with Generic Parameters Chapter A.11, Common Errors in VHDL Code ECE 448 – FPGA and ASIC Design with VHDL

Generate scheme for equations
ECE 448 – FPGA and ASIC Design with VHDL

Concurrent statements
Data-flow VHDL Major instructions Concurrent statements concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

PARITY Example

PARITY: Block Diagram

PARITY: Entity Declaration
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY parity IS PORT( parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); parity_out : OUT STD_LOGIC ); END parity;

PARITY: Block Diagram xor_out(1) xor_out(2) xor_out(3) xor_out(4)

PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: std_logic_vector (6 downto 1); BEGIN xor_out(1) <= parity_in(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); parity_out <= xor_out(6) XOR parity_in(7); END parity_dataflow;

PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (6 DOWNTO 1); BEGIN G2: FOR i IN 1 TO 7 GENERATE left_xor: IF i=1 GENERATE xor_out(i) <= parity_in(i-1) XOR parity_in(i); END GENERATE; middle_xor: IF (i >1) AND (i<7) GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); right_xor: IF i=7 GENERATE parity_out <= xor_out(i-1) XOR parity_in(i); END parity_dataflow;

PARITY: Block Diagram (2)
xor_out(0) xor_out(1) xor_out(2) xor_out(3) xor_out(4) xor_out(5) xor_out(6) xor_out(7)

PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0); BEGIN xor_out(0) <= parity_in(0); xor_out(1) <= xor_out(0) XOR parity_in(1); xor_out(2) <= xor_out(1) XOR parity_in(2); xor_out(3) <= xor_out(2) XOR parity_in(3); xor_out(4) <= xor_out(3) XOR parity_in(4); xor_out(5) <= xor_out(4) XOR parity_in(5); xor_out(6) <= xor_out(5) XOR parity_in(6); xor_out(7) <= xor_out(6) XOR parity_in(7); parity_out <= xor_out(7); END parity_dataflow;

PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0); BEGIN xor_out(0) <= parity_in(0); G2: FOR i IN 1 TO 7 GENERATE xor_out(i) <= xor_out(i-1) XOR parity_in(i); END GENERATE G2; parity_out <= xor_out(7); END parity_dataflow;

For Generate Statement
label: FOR identifier IN range GENERATE {Concurrent Statements} END GENERATE;

Conditional Generate Statement
If - Generate label: IF boolean_expression GENERATE {Concurrent Statements} END GENERATE;

Generate scheme for components

component instantiation (port map)
Structural VHDL Major instructions component instantiation (port map) component instantiation with generic (generic map, port map) generate scheme for component instantiations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

Example 1

Example 1 w 8 11 s 1 3 4 7 12 15 2 f

A 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END mux4to1 ; ARCHITECTURE Dataflow OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Dataflow ;

Straightforward code for Example 1
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Example1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END Example1 ;

ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux_l0: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; Mux_l1: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ; Mux_l2: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ; Mux_l3: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; Mux_right: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

Modified code for Example 1
ARCHITECTURE Structure OF Example1 IS COMPONENT mux4to1 PORT ( w0, w1, w2, w3 : IN STD_LOGIC ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN G1: FOR i IN 0 TO 3 GENERATE Mux_li: mux4to1 PORT MAP ( w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ; END GENERATE ; Mux_right: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

Using Dataflow Design Style
Example 1 Using Dataflow Design Style only

Example 1 w 8 11 s 1 3 4 7 12 15 2 f

LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY Example1 IS PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ; s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; f : OUT STD_LOGIC ) ; END Example1 ;

ARCHITECTURE Dataflow OF Example1 IS SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; BEGIN Mux_ri: FOR i IN 0 TO 3 GENERATE WITH s(1 downto 0) SELECT m(i) <= w(4*i) WHEN "00", w(4*i+1) WHEN "01", w(4*i+2) WHEN "10", w(4*i+3) WHEN OTHERS ; END GENERATE ; Mux_left: WITH s(3 downto 2) SELECT f <= m(0) WHEN "00", m(1) WHEN "01", m(2) WHEN "10", m(3) WHEN OTHERS ; END Dataflow ; mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ; END Structure ;

Example 2

Example 2 w w y y w w y y y y En y y w y y w y y y y w w y En y y w w
1 1 3 15 w w y y 2 14 y y 1 13 En y y 12 w y y 1 3 11 w y y 2 10 y y 1 9 w 3 w y En y y 1 3 8 w w y 2 2 y 1 En En y w w y y 1 3 7 w y y 2 6 y y 1 5 En y y 4 w y y 1 3 3 w y y 2 2 y y 1 1 En y y

A 2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END dec2to4 ; ARCHITECTURE Dataflow OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "0001" WHEN "100", "0010" WHEN "101", "0100" WHEN "110", “1000" WHEN "111", "0000" WHEN OTHERS ; END Dataflow ;

VHDL code for Example 2 (1)
LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec4to16 IS PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ; END dec4to16 ;

ARCHITECTURE Structure OF dec4to16 IS COMPONENT dec2to4 PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; Dec_r0: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(0), y(3 DOWNTO 0) ); Dec_r1: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(1), y(7 DOWNTO 4) ); Dec_r2: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(2), y(11 DOWNTO 8) ); Dec_r3: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(3), y(15 DOWNTO 12) ); END Structure ;

ARCHITECTURE Structure OF dec4to16 IS COMPONENT dec2to4 PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END COMPONENT ; SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGIN Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ; G1: FOR i IN 0 TO 3 GENERATE Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i+3 DOWNTO 4*i) ); END GENERATE ; END Structure ;

Example 3 Variable Rotator

Example 3: Variable rotator - Interface
16 4 B A <<< B 16 C ECE 448 – FPGA and ASIC Design with VHDL

Block diagram ECE 448 – FPGA and ASIC Design with VHDL

Fixed rotation <<< 3 <<< 5
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) <<< 3 y <= a(12 downto 0) & a(15 downto 13); a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11) <<< 5 y <= a(10 downto 0) & a(15 downto 11); ECE 448 – FPGA and ASIC Design with VHDL

Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15-L) a(15-L-1) a(1) a(0) a(15) a(14) a(15-L+2) a(15-L+1) <<< L y <= a(15-L downto 0) & a(15 downto 15-L+1); ECE 448 – FPGA and ASIC Design with VHDL

Array of std_logic_vectors
TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0); TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0); SIGNAL Al : array1; SIGNAL Ar : array2;

Block diagram ECE 448 – FPGA and ASIC Design with VHDL

Combinational Logic Synthesis
for Beginners ECE 448 – FPGA and ASIC Design with VHDL

Simple rules for beginners
For combinational logic, use only concurrent statements concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) ECE 448 – FPGA and ASIC Design with VHDL

For circuits composed of - simple logic operations (logic gates) - simple arithmetic operations (addition, subtraction, multiplication) - shifts/rotations by a constant use concurrent signal assignment () ECE 448 – FPGA and ASIC Design with VHDL

For circuits composed of - multiplexers - decoders, encoders - tri-state buffers use conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) ECE 448 – FPGA and ASIC Design with VHDL

For circuits with a regular structure use generate scheme for equations (for-generate) in case of simple basic components or generate scheme for components (for-generate) in case of more complex logic components. ECE 448 – FPGA and ASIC Design with VHDL

Constants ECE 448 – FPGA and ASIC Design with VHDL

Constants Examples: Syntax: CONSTANT name : type := value;
CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100"; CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4"; CONSTANT counter_width : INTEGER := 16; CONSTANT buffer_address : INTEGER := 16#FFFE#; CONSTANT clk_period : TIME := 20 ns; CONSTANT strobe_period : TIME := ms; ECE 448 – FPGA and ASIC Design with VHDL

Constants - features Constants can be declared in a
PACKAGE, ENTITY, ARCHITECTURE When declared in a PACKAGE, the constant is truly global, for the package can be used in several entities. When declared in an ARCHITECTURE, the constant is local, i.e., it is visible only within this architecture. When declared in an ENTITY declaration, the constant can be used in all architectures associated with this entity. ECE 448 – FPGA and ASIC Design with VHDL

Aliases ECE 448 – FPGA and ASIC Design with VHDL

Aliases Example: Syntax: ALIAS name : type := expression;
signal IR : std_logic_vector(31 downto 0); alias IR_opcode : std_logic_vector(5 downto 0) is IR(31 downto 26); alias IR_reg1_addr : std_logic_vector(4 downto 0) is IR(25 downto 21); alias IR_reg2_addr : std_logic_vector(4 downto 0) is IR(20 downto 16); ECE 448 – FPGA and ASIC Design with VHDL

Packages ECE 448 – FPGA and ASIC Design with VHDL

Explicit Component Declaration versus Package
Explicit component declaration is when you declare components in main code When have only a few component declarations, this is fine When have many component declarations, use packages for readability Packages also help with portability and sharing of libraries among many users in a company Remember, the actual instantiations always take place in main code Only the declarations can be in main code or package

Explicit Component Declaration Tips
For simple projects put entity .vhd files all in same directory Declare components in main code If using Aldec, make sure compiler knows the correct hierarchy From lowest to highest Xilinx will figure out hierarchy automatically

METHOD #2: Package component declaration
Components declared in package Actual instantiations and port maps always in main code

Packages Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once This makes the top-level entity code cleaner It also allows that complete package to be used by another designer A package can contain Components Functions, Procedures Types, Constants

Package – example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ;
PACKAGE GatesPkg IS COMPONENT mux2to1 PORT (w0, w1, s : IN STD_LOGIC ; f : OUT STD_LOGIC ) ; END COMPONENT ; COMPONENT priority PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ; z : OUT STD_LOGIC ) ;

Package – example (2) COMPONENT dec2to4
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; En : IN STD_LOGIC ; y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ; END COMPONENT ; COMPONENT regn GENERIC ( N : INTEGER := 8 ) ; PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ; Enable, Clock : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

Package – example (3) constant ADDAB : std_logic_vector(3 downto 0) := "0000"; constant ADDAM : std_logic_vector(3 downto 0) := "0001"; constant SUBAB : std_logic_vector(3 downto 0) := "0010"; constant SUBAM : std_logic_vector(3 downto 0) := "0011"; constant NOTA : std_logic_vector(3 downto 0) := "0100"; constant NOTB : std_logic_vector(3 downto 0) := "0101"; constant NOTM : std_logic_vector(3 downto 0) := "0110"; constant ANDAB : std_logic_vector(3 downto 0) := "0111"; END GatesPkg;

Package usage (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ;
USE work.GatesPkg.all; ENTITY priority_resolver1 IS PORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ; s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ; clk : IN STD_LOGIC; en : IN STD_LOGIC; t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ; END priority_resolver1; ARCHITECTURE structural OF priority_resolver1 IS SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ; SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ; SIGNAL ena : STD_LOGIC ;

Package usage (2) BEGIN u1: mux2to1 PORT MAP ( w0 => r(0) ,
s => s(0), f => p(0)); p(1) <= r(2); p(2) <= r(3); u2: mux2to1 PORT MAP ( w0 => r(4) , w1 => r(5), s => s(1), f => p(3)); u3: priority PORT MAP ( w => p, y => q, z => ena); u4: dec2to4 PORT MAP ( w => q, En => ena, y => z); u5: regn GENERIC MAP ( N => 4) PORT MAP ( D => z , Enable => En , Clock => Clk, Q => t ); END structural;

Aldec Compilation Order
Include package before top-level

ECE 448 Lecture 4 Modeling of Circuits with a Regular Structure Constants, Aliases, Packages ECE 448 – FPGA and ASIC Design with VHDL.

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ECE 448 Lecture 4 Modeling of Circuits with a Regular Structure Constants, Aliases, Packages ECE 448 – FPGA and ASIC Design with VHDL.

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Presentation on theme: "ECE 448 Lecture 4 Modeling of Circuits with a Regular Structure Constants, Aliases, Packages ECE 448 – FPGA and ASIC Design with VHDL."— Presentation transcript:

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