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The Verilog Hardware Description Language
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Example Describe a 5-bit multiplier in Verilog.
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Conditional assignment - describing MUXs
assign = select_signal ? assignment1 : assignment1 module mux (o, s, i0, i1); output o; input i0, i1; input s; assign o = s ? i1 : i0; //if s =1 then o = i1, else o =i0 endmodule
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Cyclic behavior Statements in cyclic behavior execute sequentially
Can be used to describe either combinational circuits (optional) or sequential circuits (only way) always & (sensitivity list) begin sequential statements end
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Combinational Circuit Description using Cyclic Behavior
(a or b or c) begin d = (a & b) | c; end ALL input signals must be in sensitivity list or latches will be produced!
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If statement (sequential)– describing MUXs
if (condition1) begin signal1 <= value1; signal2 <= value2; end else if (condition2) begin signal1 <= value3; signal2 <= value4; … else begin signal1 <= valuen-1; signal2 <= valuen; module mux (o, s, i0, i1); output o; reg o; input i0, i1; input s; (i0 or i1 or s) begin if (s == 0) o = i0; else o = i1; end endmodule
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CASE statement (sequential)– describing MUXs
module mux (o, s, i0, i1); output o; reg o; input i0, i1; input s; (i0 or i1 or s) begin case (s) 0: o = i0; 1: o = i1; default: o= 1’bx; endcase end endmodule case (signal) value1: signal1 <= value2; signal2 <= value3; value2 : signal1 <= value4; signal2 <= value5; default: signal1 <= valuen-1; signal2 <= valuen; endcase
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Example Describe a 3-bit 4-to-1 MUX
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CLOCKED PROCESS (Latch with asynchronous reset)
(clk or rst_n) begin if (rst_n == 0) q <= 0; else if (clk == 1) q <= d; end
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CLOCKED PROCESS (Latch with synchronous reset)
(clk or rst_n) begin if (clk == 1) q <= d; else if (rst_n == 0) q <= 0; end
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CLOCKED PROCESS (Flip-flop with asynchronous reset)
clk or negedge rst_n) begin if (rst_n == 0) q <= 0; else q <= d; end
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CLOCKED PROCESS (Flip-flop with synchronous reset)
clk) begin if (rst_n == 0) q <= 0; else q <= d; end
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for loop statement – shift register
module shift_reg (o, clk, rst_n, i); output o; input i; input clk, rst_n; reg [3:0] d; integer k; (posedge clk or negedge rst_n) begin if (rst_n ==0) d <= 0; else d[0] <= i; for (k=0; k <4; k=k+1) d[k+1] <= d[k]; end assign o = d[3]; endmodule
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CLOCKED VS COMBINATIONAL PROCESS (1/2)
(posedge clk or negedge rst_n) begin if (rst_n == 0) q <= 0; else case (c) 0: q = a; 1: q = b; default: q= 1’bx; endcase end (a or b or c) begin case (c) 0: q = a; 1: q = b; default: q= 1’bx; endcase end
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CLOCKED VS COMBINATIONAL PROCESS (2/2)
(a or b or c) begin d = (a & b) | c; end (posedge clk) begin if (rst_n == 0) d <= 0; else d <= (a & b) | c; end
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EXAMPLE DESCIBE A BINARY UP/DOWN COUNTER WITH ENABLE THAT COUNTS UPTO 12 AND THEN STARTS AGAIN FROM ZERO
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TESTBENCH `timescale 1ns / 100ps module testbench_name (); reg ….; //declaration of register variables for DUT inputs wire …; //declaration of wires for DUT outputs DUT_name(DUT ports); initial $monitor(); //signals to be monitored (optional) initial begin #100 $finish; //end simulation end initial begin clk = 1’b0; //initialize clk #10 a = 0; #10 a = 1; … always # 50 clk = ~clk; //50 ns clk period (if there is a clock) endmodule
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TESTBENCH EXAMPLE `timescale 1ns / 100ps module mux_tb (); reg i0, i1, s; wire o; mux M1 (o, s, i0, i1); initial begin #100 $finish; //end simulation end initial begin //stimulus pattern #10 i0 = 0; i1=0; s=0; #10 i0=1; #10 i0 = 0; i1=1; #10 i0=0; i1= 0; s=1; end endmodule
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FINITE STATE MACHINES
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FINITE STATE MACHINE IMPLEMENTATION
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Mealy machines (1/5) module fsm (y, clk, rst_n, x); output y;
input clk, rst_n, x; reg [1:0] state_pr, state_nx; parameter a = 0, b = 1, c = 2, d = 3, dont_care_state = 2’bx, dont_care_out = 1’bx;
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Mealy machines (2/5) (posedge clk or negedge rst_n) //state memory begin if (rst_n == 0) state_pr <= a; //default state else state_pr <= state_nx; end
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Mealy machines (3/5) (x or state_pr) //combinational part begin CASE (state_pr) a: if (x == 1) begin state_nx <= b; y <= 1’b0; end else if (x == 0) begin state_nx <= a; --optional
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Mealy machines (4/5) b: if (x == 1) begin state_nx = c; output <= 1’b0; --Mealy machine end else if (x==0) begin state_nx <= a; output <= 1’b0 ; --Mealy machine c: if (x == 1) begin state_nx = c; --optional else if x==0) begin state_nx <= d;
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Mealy machines (5/5) d: if (x == 1) begin state_nx = b; output <= 1’b1; --Mealy machine end else if (x==0) begin state_nx <= a; output <= 1’b0 ; --Mealy machine default: begin next_state = dont_care_state; y <= dont_care_out; endcase endmodule
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Moore machines (a or state_pr) --combinational part begin CASE (state_pr) s0: y <= <value>; --Moore machine if (a == 1) state_nx <= s1; else state_nx <= s0; --optional
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MOORE MACHINES S1: y <= <value>; --Moore machine if (a == 1) state_nx <= S0; else state_nx <= S1; --optional endcase end
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EXAMPLE: OUT-OF-SEQUENCE COUNTER
DESCRIBE A COUNTER WITH THE FOLLOWING SEQUENCE: “000” => “010” => “011” => “001” => “111” => “000”
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