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Based on Xilinx ISE & ModelSim

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Presentation on theme: "Based on Xilinx ISE & ModelSim"— Presentation transcript:

1 Based on Xilinx ISE & ModelSim
ECE 448: Spring 11 Lab 4 – Part 1 Finite State Machines FPGA Design Flow Based on Xilinx ISE & ModelSim Add design flow from lecture 1 Why are we interested in PRNG Generate with R=8 Reduce PRNG to 3 slides: purpose, GIF, example Add Loading circuit for PRNG

2 Agenda for today Part 1: Introduction to the new Lab Assignment:
Bus Ticket Dispensing Machine. Part 2: FPGA Design Flow based on Xilinx ISE and ModelSim Part 3: Demos of Lab 3 2

3 Rising Edge Detector 3

4 Rising Edge Detector Turn a step function into an impulse
Allows a step to run a circuit for only one clock cycle

5 Rising Edge Detector - RED
data_i data_o clk_i clk_i data_i data_o

6 Rising Edge Detectors (REDs)

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