1. CSE 201 Computer Logic Design * * * * * * * Verilog Modeling
Basics
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

2. Two Primary Ways of Modeling Logic
Structural
Behavioral
DO NOT use “always”
Use “always” block
Outputs declared as “wire”
Outputs declared as “reg”
“Schematics using text”
“Instantiate” other modules
and interconnect them with
wires and busses…
Combinational Logic
Sequential Logic
… or, alternatively,
use the “assign” statement along with the verilog operators for “and” (&), “or” (|), “not” (~) and xor (^).
(*)
(posedge clk, posedge reset)
case ( {all inputs} )
if ( reset == 1’b1 ) //check for reset first
// assign output(s) for reset condition
// each row assigns output(s)
// based on input combinations
else //got a clock
// assign output(s) based on decisions
For example, assign F1 = (~W & X & ~Y) | (~X & ~Z);
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

3. Fundamentals Verilog Module Definitions (structural)
Module name (must begin with a letter or underscore)
Port list (input and output names)
module addsub4 ( M, A, B, Cin, Y, CB );
input [3:0] A, B;
input M, Cin;
output wire [3:0] Y;
output wire CB;
input/output declarations
size specifier (default size is 1-bit scalar)
type specifier (for outputs only, default type is wire)
// structural logic of 4-bit add/sub
// using 4 instances of 1-bit addsub
addsub a0 ( M, A[0], B[0], Cin, Y[0], cb0),
a1 ( M, A[1], B[1], cb0, Y[1], cb1),
a2 ( M, A[2], B[2], cb1, Y[2], cb2),
a3 ( M, A[3], B[3], cb2, Y[3], CB);
single line comments
endmodule
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

4. Fundamentals Verilog Module Definitions (behavioral)
Module name (must begin with a letter or underscore)
Port list (input and output names)
module addsub ( M, A, B, Cin, Y, CB );
input [3:0] A, B;
input M, Cin;
output reg [3:0] Y;
output reg CB;
input/output declarations
size specifier (default size is 1-bit scalar)
type specifier (for outputs only)
event operator
sensitivity list
always @ ( M, A, B, Cin ) begin
// behavioral logic of add/sub
if ( M == 1’b0 )
{CB,Y} = A + B + Cin;
else
{CB,Y} = A - B - Cin;
single line comment
Note: Verilog is an “event driven” language,
not a “sequential” language.
concatenation operator
As such, the most powerful operator in the
verilog language is the “event” operator
end // end of always
endmodule
In practical use, the second most powerful
operator is the concatenation operator ( { , } ).
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

5. Structural Verilog Module Example (2-to-4 decoder)En Y3 Y2 Y1 Y0
decode_2to4
One could create four 3-variable K-maps to
find the S.O.P expressions for the four outputs,
but, by observation, each output only has one
minterm in the truth table where it is “1.”
En I1 I0 Y3 Y2 Y1 Y0
Thus, Y3 = En & I1 & I0
Y2 = En & I1 & I0’
Y1 = En & I1’ & I0
Y2 = En & I1’ & I0’
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

6. Structural Verilog Module Example (2-to-4 decoder)
Thus, Y3 = En & I1 & I0
Y2 = En & I1 & I0’
Y1 = En & I1’ & I0
Y2 = En & I1’ & I0’
Structural using “gates”
module decoder_2to4 (En, I1, I0, Y3, Y2, Y1, Y0);
input En, I1, I0;
output wire Y3, Y2, Y1, Y0;
wire i1_n, i0_n; // interconnection wires for not gate outputs
// Structural model of decoder using 4 3-input “and” gates
not n1 (i1_n, I1),
n0 (i0_n, I0);
and ag3 (Y3, En, I1, I0),
ag2 (Y2, En, I1, i0_n),
ag1 (Y1, En, i1_n, I0),
ag0 (Y0, En, i1_n, i0_n);
endmodule
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

7. Structural Verilog Module Example (2-to-4 decoder)
Thus, Y3 = En & I1 & I0
Y2 = En & I1 & I0’
Y1 = En & I1’ & I0
Y2 = En & I1’ & I0’
Structural using “assign”
module decoder_2to4 (En, I1, I0, Y3, Y2, Y1, Y0);
input En, I1, I0;
output wire Y3, Y2, Y1, Y0;
// Structural model of decoder using 4 3-input “assign” statement
assign Y3 = (En & I1 & I0),
Y2 = (En & I1 & ~I0),
Y1 = (En & ~I1 & I0),
Y0 = (En & ~I1 & ~I0);
endmodule
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

8. Behavioral Verilog Module Example (2-to-4 decoder)En Y3 Y2 Y1 Y0
decode_2to4
Having the truth table for ANY logic function,
we can create a “behavioral” module using the
verilog “case statement.”
In essence, the “case statement” has exactly the
same input/output relationships seen in a table;
yet the table data must be placed in the case “template.”
// behavioral logic of 2-to-4 decoder
case ( {En, I1, I0} )
3’b000: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b001: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b010: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b011: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b100: {Y3,Y2,Y1,Y0} = 4’b0001;
3’b101: {Y3,Y2,Y1,Y0} = 4’b0010;
3’b110: {Y3,Y2,Y1,Y0} = 4’b0100;
3’b111: {Y3,Y2,Y1,Y0} = 4’b1000;
endcase
En I1 I0 Y3 Y2 Y1 Y0
Inputs
Outputs
CSULB -- CECS 201– Verilog Basics
© R.W. Allison

9. Behavioral Verilog Module Example (2-to-4 decoder)
The “case statement” must be placed within the verilog “always” block, the only procedural block used in behavioral modeling.
The complete module is created by “packaging” the procedural block within the applicable verilog module declarations ...
module decoder_2to4 ( En, I1, I0, Y3, Y2, Y1, Y0);
input En, I1, I0;
output reg Y3, Y2, Y1, Y0;
endmodule
// Although verilog allows for “free
// formatting,” you are encouraged to
// develop good coding style.
case ( {En, I1, I0} )
3’b000: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b001: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b010: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b011: {Y3,Y2,Y1,Y0} = 4’b0000;
3’b100: {Y3,Y2,Y1,Y0} = 4’b0001;
3’b101: {Y3,Y2,Y1,Y0} = 4’b0010;
3’b110: {Y3,Y2,Y1,Y0} = 4’b0100;
3’b111: {Y3,Y2,Y1,Y0} = 4’b1000;
endcase
// behavioral logic of 2-to-4 decoder
(En, I1, I0) begin
end // end of always block
// “Programming styles commonly deal
// with the visual appearance of source
// code, with the goal of requiring less
// human cognitive effort to extract
// information about the program.”1
1 ref
CSULB -- CECS 201– Verilog Basics
© R.W. Allison