1. Electrical and Computer Engineering
EEL 5764: Graduate Computer Architecture Appendix C – Memory Hierarchy Review
Ann Gordon-Ross
Electrical and Computer Engineering
University of Florida
These slides are provided by:
David Patterson
Electrical Engineering and Computer Sciences, University of California, Berkeley
Modifications/additions have been made from the originals
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2. Since 1980, CPU has outpaced DRAM ...
Q. How do architects address this gap?
A. Put smaller, faster “cache” memories between CPU and DRAM.
Create a “memory hierarchy”.
Performance
(1/latency)
CPU
60% per yr
2X in 1.5 yrs
1000
CPU
Gap grew 50% per year
100
DRAM
9% per yr
2X in 10 yrs 10
RamBus
Solution to gap = caches
DRAM
1980
1990
2000
Year
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3. 1977: DRAM faster than microprocessors
Apple ][ (1977)
Steve
Wozniak
Steve Jobs
CPU: 1000 ns
DRAM: 400 ns
Old days….
No cache
CPU slower than DRAM
No worries
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4. Levels of the Memory Hierarchy
Upper Level
Capacity
Access Time
Cost
Staging
Xfer Unit
faster
CPU Registers
100s Bytes
<10s ns
Registers
Instr. Operands
prog./compiler
1-8 bytes
Cache
K Bytes ns
1-0.1 cents/bit
Cache
cache cntl
8-128 bytes
Blocks
Main Memory
M Bytes
200ns- 500ns
$ cents /bit
Memory OS
512-4K bytes
Pages
Disk
G Bytes, 10 ms (10,000,000 ns)
cents/bit
Memory hierarchy has been talked about forever
Disk -5 -6
user/operator
Mbytes
Files
Tape
infinite
sec-min 10
Larger
Tape
Lower Level -8
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5. Memory Hierarchy: Apple iMac G5
1.6 GHz
Managed
by compiler
Managed
by hardware
Managed by OS,
hardware,
application 07
Reg
L1 Inst
L1 Data L2
DRAM
Disk
Size 1K
64K
32K
512K
256M
80G
Latency
Cycles, Time 1,
0.6 ns 3,
1.9 ns
11,
6.9 ns
88,
55 ns
107,
12 ms
Goal: Illusion of large, fast, cheap memory
20 years later, but this is a couple years old
Create illusion of fast, large, cheap memory
Let programs address a memory space that scales to the disk size, at a speed that is usually as fast as register access
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6. iMac’s PowerPC 970: All caches on-chip
L1 (64K Instruction)
(1K)
Registers
512K L2
Registers are large because they are dual ported
L2 is denser so not so big
Just bits, no control logic
Memory 1/2 of chip
Some with L3 cache
L1 (32K Data)
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7. The Principle of Locality
Program access a relatively small portion of the address space at any instant of time.
Two Different Types of Locality:
Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon (e.g., loops, reuse)
Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon (e.g., straightline code, array access)
Last 15 years, HW relied on locality for speed
Why caches stick around??
Cuz of locality, why? Could be the nature of how we program, but this may change one day
It is a property of programs which is exploited in machine design.
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8. Programs with locality cache well ...
Bad locality behavior
Temporal
Locality
Memory Address (one dot per access)
Case for virtual memory, collected data at IBM
Spatial
Locality
Donald J. Hatfield, Jeanette Gerald: Program Restructuring for Virtual Memory. IBM Systems Journal 10(3): (1971)
Time
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9. Memory Hierarchy: Terminology
Hit: data appears in some block in the upper level (example: Block X)
Hit Rate: the fraction of memory access found in the upper level
Hit Time: Time to access the upper level which consists of
RAM access time + Time to determine hit/miss
Miss: data needs to be retrieve from a block in the lower level (Block Y)
Miss Rate = 1 - (Hit Rate)
Miss Penalty: Time to replace a block in the upper level +
Time to deliver the block the processor
Hit Time << Miss Penalty (500 instructions)
May be better to recalculate results instead of refetching
Lower Level
Memory
Upper Level
To Processor
From Processor
Blk X
Blk Y
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10. Cache Measures Hit rate: fraction found in that level
So high that usually talk about Miss rate
Miss rate fallacy: as MIPS to CPU performance, miss rate to average memory access time in memory
Average memory-access time = Hit time + Miss rate x Miss penalty (ns or clocks)
Miss penalty: time to replace a block from lower level, including time to replace in CPU
access time: time to lower level
= f(latency to lower level)
transfer time: time to transfer block
=f(BW between upper & lower levels)
Average memory access time is a better measurement
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11. 4 Questions for Memory Hierarchy
Q1: Where can a block be placed in the upper level? (Block placement)
Q2: How is a block found if it is in the upper level? (Block identification)
Q3: Which block should be replaced on a miss? (Block replacement)
Q4: What happens on a write? (Write strategy)
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12. Q1: Where can a block be placed in the upper level?
Block 12 placed in 8 block cache:
Fully associative, direct mapped, 2-way set associative
S.A. Mapping = Block Number Modulo Number Sets
Direct Mapped
(12 mod 8) = 4
2-Way Assoc
(12 mod 4) = 0
Full Mapped
Cache
Memory
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13. Q2: How is a block found if it is in the upper level?
Tag on each block
No need to check index or block offset
Increasing associativity shrinks index, expands tag
Block
Offset
Block Address
Index
Tag
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14. Q3: Which block should be replaced on a miss?
Easy for Direct Mapped
Set Associative or Fully Associative:
Random
LRU (Least Recently Used)
Assoc: way way way
Size LRU Ran LRU Ran LRU Ran
16 KB 5.2% 5.7% % 5.3% 4.4% 5.0%
64 KB 1.9% 2.0% % 1.7% 1.4% 1.5%
256 KB 1.15% 1.17% % % % %
LRU - Becomes more complicated as associativity goes up - more hardware required
Usually use random for high associativities
Random and LRU perform close
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15. Q4: What happens on a write?
Write-Through
Write-Back
Policy
Data written to cache block
also written to lower-level memory
Write data only to the cache
Update lower level when a block falls out of the cache
Debug
Easy
Hard
Do read misses produce writes? No
Yes
Do repeated writes make it to lower level?
What do you do on write miss? Write allocate or write no-allocate
Additional option -- let writes to an un-cached address allocate a new cache line (“write-allocate”).
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16. Write Buffers for Write-Through Caches
Processor
Cache
Write Buffer
Lower Level Memory
Holds data awaiting write-through to
lower level memory
Q. Why a write buffer ?
A. So CPU doesn’t stall
Q. Why a buffer, why not just one register ?
A. Bursts of writes are
common.
To reduce traffic and eliminate CPU wait time
Q. Are Read After Write (RAW) hazards an issue for write buffer?
A. Yes! Drain buffer before next read, or send read 1st after check write buffers.
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17. 5 Basic Cache Optimizations
Reducing Miss Rate
Larger Block size (compulsory misses)
Larger Cache size (capacity misses)
Higher Associativity (conflict misses)
Reducing Miss Penalty
Multilevel Caches
Reducing hit time
Giving Reads Priority over Writes
E.g., Read complete before earlier writes in write buffer
2,3 can effect hit time
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18. Outline Memory hierarchy Locality Cache design Virtual address spaces
Page table layout
TLB design options
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19. The Limits of Physical Addressing
“Physical addresses” of memory locations
Data
All programs share one address space:
The physical address space
A0-A31
A0-A31
CPU
Memory
D0-D31
D0-D31
Nothing to stop program from screwing up another program
Programmers used to have to figure out how to fit program in memory and manually load parts in and out as needed
Machine language programs must be
aware of the machine organization
No way to prevent a program from accessing any machine resource
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20. Solution: Add a Layer of Indirection
“Physical Addresses”
Address
Translation
Virtual
Physical
“Virtual Addresses”
A0-A31
A0-A31
CPU
Memory
D0-D31
D0-D31
Data
User programs run in an standardized
virtual address space
Solve with indirection
Each user how has their own address space
Otherwise OS has to figure out when and who can access parts of memory
Could change grades
Provides protection
Allow for memory to appear bigger
Address Translation hardware
managed by the operating system (OS)
maps virtual address to physical memory
Hardware supports “modern” OS features:
Protection, Translation, Sharing
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21. Three Advantages of Virtual Memory
Translation:
Program can be given consistent view of memory, even though physical memory is scrambled
Makes multithreading reasonable (now used a lot!)
Only the most important part of program (“Working Set”) must be in physical memory.
Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow later.
Protection:
Different processes protected from each other.
Different pages can be given special behavior
(Read Only, Invisible to user programs, etc).
Kernel data protected from User programs
Very important for protection from malicious programs
Sharing:
Can map same physical page to multiple users (“Shared memory”)
Original goals - put the important part in memory, rest on disk
Now there is more memory so main goals have changed
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22. Page tables encode virtual address spaces
A virtual address space
is divided into blocks
of memory called pages
Physical
Address Space
Virtual
frame
A machine usually supports
pages of a few sizes
(MIPS R4000):
frame
frame
frame
Page based memory
Mapping (page table) between virtual and physical address space
A valid page table entry codes physical memory “frame” address for the page
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23. Page tables encode virtual address spaces
OS manages the page table for each ASID
Physical
Memory Space
A valid page table entry codes physical memory “frame” address for the page
A virtual address space
is divided into blocks
of memory called pages
frame
frame
frame
A machine usually supports
pages of a few sizes
(MIPS R4000):
frame
A page table is indexed by a
virtual address
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24. Details of Page Table
Page Table
Physical
Memory Space
Virtual Address
Page Table
index
into
page
table
Base Reg V
Access
Rights PA
V page no.
offset 12
table located
in physical
memory
P page no.
Physical Address
frame
frame
frame
frame
virtual address
This is where access rights are checked
Page table maps virtual page numbers to physical frames (“PTE” = Page Table Entry)
Virtual memory => treat memory  cache for disk
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25. Page tables may not fit in memory!
A table for 4KB pages for a 32-bit address space has 1M entries
Each process needs its own address space!
Two-level Page Tables
P1 index
P2 index
Page Offset 31 12 11 21 22
32 bit virtual address
Multi-level page tables to save space if page tables too big
Top-level table wired in main memory
Subset of 1024 second-level tables in main memory; rest are on disk or unallocated
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26. VM and Disk: Page replacement policy
...
Page Table
used
dirty
Dirty bit: page written.
Used bit: set to
1 on any reference
Set of all pages
in Memory
Tail pointer:
Clear the used
bit in the
page table
Head pointer
Place pages on free list if used bit
is still clear.
Schedule pages with dirty bit set to
be written to disk.
Freelist
Free Pages
Ring model, check pages
Architect’s role: support setting dirty and used bits
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27. MIPS Address Translation: How does it work?
“Virtual Addresses”
“Physical Addresses”
A0-A31
Virtual
Physical
A0-A31
Translation
Look-Aside
Buffer
(TLB)
Translation Look-Aside Buffer (TLB)
A small fully-associative cache of
mappings from virtual to physical addresses
CPU
Memory
D0-D31
D0-D31
Data
What is the table of
mappings that it caches?
Now each memory access could take twice as long - page fault and fetch data
TLB also contains
protection bits for virtual address
Fast common case: Virtual address is in TLB,
process has permission to read/write it.
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