1. ECE 448 Lab 1 Developing Effective Testbenches
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University

2. Agenda for today Part 1: Lab Rules
Part 2: Installation and Setup of Tools
Part 3: Refresher on Simple Testbenches
Part 4: Introduction to Lab 1
Part 5a: Hands-on Session: ISim Tutorial
Part 5b: Hands-on Session: Class Exercise

3. Part 1
Lab Rules
ECE 448 – FPGA and ASIC Design with VHDL

4. Installation and Setup of Tools
Part 2
Installation and Setup of Tools
ECE 448 – FPGA and ASIC Design with VHDL

5. Refresher on VHDL Testbenches
Part 3
Refresher on VHDL Testbenches
ECE 448 – FPGA and ASIC Design with VHDL

6. Design Under Test (DUT)
Simple Testbench
Processes
Generating
Stimuli
Design Under Test (DUT)
Verify simulated outputs with expected output to see if the design behaves according to specification
Observed Outputs
ECE 448 – FPGA and ASIC Design with VHDL

7. Testbench Defined
Testbench = VHDL entity that applies stimuli (drives the inputs) to the Design Under Test (DUT) and (optionally) verifies expected outputs.
The results can be viewed in a waveform window or written to a file.
Since Testbench is written in VHDL, it is not restricted to a single simulation tool (portability).
The same Testbench can be easily adapted to test different implementations (i.e., different architectures) of the same design.
ECE 448 – FPGA and ASIC Design with VHDL

8. Possible sources of expected results used for comparison
Testbench
actual results
VHDL Design
= ?
Representative
Inputs
Manual Calculations or
Reference Software Implementation (C, Java, Matlab )
expected results
ECE 448 – FPGA and ASIC Design with VHDL

9. Test vectors Set of pairs: {Input Values i, Expected Outputs Values i}
Input Values 1, Expected Output Values 1
Input Values 2, Expected Output Values 2
……………………………
Input Values N, Expected Output Values N
Test vectors can cover either:
- all combinations of inputs (for very simple circuits only)
- selected representative combinations of inputs
(most realistic circuits)
ECE 448 – FPGA and ASIC Design with VHDL

10. Testbench The same testbench can be used to
test multiple implementations of the same circuit
(multiple architectures)
testbench
design entity
Architecture 1
Architecture 2
Architecture N
ECE 448 – FPGA and ASIC Design with VHDL

11. Testbench Anatomy ENTITY my_entity_tb IS --TB entity has no ports
END my_entity_tb;
ARCHITECTURE behavioral OF tb IS
--Local signals and constants
BEGIN
DUT: entity work.TestComp PORT MAP( Instantiations of DUTs );
testSequence: PROCESS
-- Input stimuli
END PROCESS;
END behavioral;
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
ECE 448 – FPGA and ASIC Design with VHDL

12. Testbench for XOR3 (1) LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY xor3_tb IS
END xor3_tb;
ARCHITECTURE behavioral OF xor3_tb IS
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
SIGNAL test_vector: STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL test_result : STD_LOGIC;
ECE 448 – FPGA and ASIC Design with VHDL

13. Testbench for XOR3 (2) ECE 448 – FPGA and ASIC Design with VHDL BEGIN
UUT : entity work.xor3
PORT MAP (
A => test_vector(2),
B => test_vector(1),
C => test_vector(0),
Result => test_result); );
Testing: PROCESS
test_vector <= "000";
WAIT FOR 10 ns;
test_vector <= "001";
test_vector <= "010";
test_vector <= "011";
test_vector <= "100";
test_vector <= "101";
test_vector <= "110";
test_vector <= "111";
END PROCESS;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

14. VHDL Design Styles VHDL Design Styles dataflow structural behavioral
Concurrent
statements
Components and
interconnects
Sequential statements
Testbenches
ECE 448 – FPGA and ASIC Design with VHDL

15. Process without Sensitivity List and its use in Testbenches
ECE 448 – FPGA and ASIC Design with VHDL

16. What is a PROCESS?
A process is a sequence of instructions referred to as sequential statements.
The keyword PROCESS
A process can be given a unique name using an optional LABEL
This is followed by the keyword PROCESS
The keyword BEGIN is used to indicate the start of the process
All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important.
A process must end with the keywords END PROCESS.
Testing: PROCESS
BEGIN
test_vector<=“00”;
WAIT FOR 10 ns;
test_vector<=“01”;
test_vector<=“10”;
test_vector<=“11”;
END PROCESS;
ECE 448 – FPGA and ASIC Design with VHDL

17. Execution of statements in a PROCESS
Testing: PROCESS
BEGIN
test_vector<=“00”;
WAIT FOR 10 ns;
test_vector<=“01”;
test_vector<=“10”;
test_vector<=“11”;
END PROCESS;
The execution of statements continues sequentially till the last statement in the process.
After execution of the last statement, the control is again passed to the beginning of the process.
Order of execution
Program control is passed to the first statement after BEGIN
ECE 448 – FPGA and ASIC Design with VHDL

18. PROCESS with a WAIT Statement
The last statement in the PROCESS is a WAIT instead of WAIT FOR 10 ns.
This will cause the PROCESS to suspend indefinitely when the WAIT statement is executed.
This form of WAIT can be used in a process included in a testbench when all possible combinations of inputs have been tested or a non-periodical signal has to be generated.
Testing: PROCESS
BEGIN
test_vector<=“00”;
WAIT FOR 10 ns;
test_vector<=“01”;
test_vector<=“10”;
test_vector<=“11”;
WAIT;
END PROCESS;
Order of execution
Program execution stops here
ECE 448 – FPGA and ASIC Design with VHDL

19. WAIT FOR vs. WAIT
WAIT FOR: waveform will keep repeating itself forever … 1 2 3 1 2 3
WAIT : waveform will keep its state after the last wait instruction. …
ECE 448 – FPGA and ASIC Design with VHDL

20. Specifying time in VHDL
ECE 448 – FPGA and ASIC Design with VHDL

21. Time values (physical literals) - Examples
7 ns
1 min
min
10.65 us
10.65 fs
unit of time
most commonly
used in simulation
Numeric value
Space
(required)
Unit of time
ECE 448 – FPGA and ASIC Design with VHDL

22. Units of time Unit Definition Base Unit
fs femtoseconds (10-15 seconds)
Derived Units
ps picoseconds (10-12 seconds)
ns nanoseconds (10-9 seconds)
us microseconds (10-6 seconds)
ms miliseconds (10-3 seconds)
sec seconds
min minutes (60 seconds)
hr hours (3600 seconds)
ECE 448 – FPGA and ASIC Design with VHDL

23. Simple Testbenches
ECE 448 – FPGA and ASIC Design with VHDL

24. Generating selected values of one input
SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);
BEGIN
testing: PROCESS
test_vector <= "000";
WAIT FOR 10 ns;
test_vector <= "001";
test_vector <= "010";
test_vector <= "011";
test_vector <= "100";
END PROCESS;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

25. Generating all values of one input
USE ieee.std_logic_unsigned.all;
SIGNAL test_vector : STD_LOGIC_VECTOR(3 downto 0):="0000";
BEGIN
testing: PROCESS
WAIT FOR 10 ns;
test_vector <= test_vector + 1;
end process TESTING;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

26. Arithmetic Operators in VHDL (1)
To use basic arithmetic operations involving
std_logic_vectors you need to include the
following library packages:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all; or
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
ECE 448 – FPGA and ASIC Design with VHDL

27. Arithmetic Operators in VHDL (2)
You can use standard +, - operators
to perform addition and subtraction:
signal A : STD_LOGIC_VECTOR(3 downto 0);
signal B : STD_LOGIC_VECTOR(3 downto 0);
signal C : STD_LOGIC_VECTOR(3 downto 0); ……
C <= A + B;
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
ECE 448 – FPGA and ASIC Design with VHDL

28. Different ways of performing the same operation
signal count: std_logic_vector(7 downto 0);
You can use:
count <= count + " "; or
count <= count + 1;
count <= count + '1';
ECE 448 – FPGA and ASIC Design with VHDL

29. Different declarations for the same operator
Declarations in the package ieee.std_logic_unsigned:
function “+” ( L: std_logic_vector; R: std_logic_vector ) return std_logic_vector;
function “+” ( L: std_logic_vector; R: integer ) return std_logic_vector;
function “+” ( L: std_logic_vector; R: std_logic ) return std_logic_vector;
ECE 448 – FPGA and ASIC Design with VHDL

30. Operator overloading
Operator overloading allows different argument types for a given operation (function)
The VHDL tools resolve which of these functions to select based on the types of the inputs
This selection is transparent to the user as long as the function has been defined for the given argument types.
ECE 448 – FPGA and ASIC Design with VHDL

31. Library inclusion
When dealing with unsigned arithmetic use: LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
When dealing with signed arithmetic use:
LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all;
When dealing with both unsigned and signed arithmetic use:
LIBRARY IEEE; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all;
 Then, do all type conversions explicitly

32. std_logic_unsigned vs. std_logic_arith
UNSIGNED ADDER WITH NO CARRYOUT
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto0) );
end adder;
architecture adder_arch of adder is
begin
c <= a + b;
end adder_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0) );
end adder;
architecture adder_arch of adder is
begin
c <= std_logic_vector(unsigned(a) unsigned(b));
end adder_arch;
Tells compiler to treat std_logic_vector like unsigned type

33. std_logic_signed vs. std_logic_arith
SIGNED ADDER
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_signed.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto0));
end adder;
architecture adder_arch of adder is
begin
c <= a + b;
end adder_arch;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
entity adder is
port(
a : in STD_LOGIC_VECTOR(2 downto 0);
b : in STD_LOGIC_VECTOR(2 downto 0);
c : out STD_LOGIC_VECTOR(2 downto 0));
end adder;
architecture adder_arch of adder is
begin
c <= std_logic_vector(signed(a) signed(b));
end adder_arch;
Tells compiler to treat std_logic_vector like signed type

34. Generating all possible values of two inputs
USE ieee.std_logic_unsigned.all;
SIGNAL test_ab : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL test_sel : STD_LOGIC_VECTOR(1 downto 0);
BEGIN
double_loop: PROCESS
test_ab <="00";
test_sel <="00";
for I in 0 to 3 loop
for J in 0 to 3 loop
wait for 10 ns;
test_ab <= test_ab + 1;
end loop;
test_sel <= test_sel + 1;
END PROCESS;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

35. Generating periodical signals, such as clocks
CONSTANT clk1_period : TIME := 20 ns;
CONSTANT clk2_period : TIME := 200 ns;
SIGNAL clk1 : STD_LOGIC;
SIGNAL clk2 : STD_LOGIC := ‘0’;
BEGIN
clk1_generator: PROCESS
clk1 <= ‘0’;
WAIT FOR clk1_period/2;
clk1 <= ‘1’;
END PROCESS;
clk2 <= not clk2 after clk2_period/2;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

36. Generating one-time signals, such as resets
CONSTANT reset1_width : TIME := 100 ns;
CONSTANT reset2_width : TIME := 150 ns;
SIGNAL reset1 : STD_LOGIC;
SIGNAL reset2 : STD_LOGIC := ‘1’;
BEGIN
reset1_generator: PROCESS
reset1 <= ‘1’;
WAIT FOR reset1_width;
reset1 <= ‘0’;
WAIT;
END PROCESS;
reset2_generator: PROCESS
WAIT FOR reset2_width;
reset2 <= ‘0’;
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

37. Typical error SIGNAL test_vector : STD_LOGIC_VECTOR(2 downto 0);
SIGNAL reset : STD_LOGIC;
BEGIN
generator1: PROCESS
reset <= ‘1’;
WAIT FOR 100 ns
reset <= ‘0’;
test_vector <="000";
WAIT;
END PROCESS;
generator2: PROCESS
WAIT FOR 200 ns
test_vector <="001";
WAIT FOR 600 ns
test_vector <="011";
END behavioral;
ECE 448 – FPGA and ASIC Design with VHDL

38. Asserts and Reports
ECE 448 – FPGA and ASIC Design with VHDL

39. Assert Assert is a non-synthesizable statement
whose purpose is to write out messages
on the screen when problems are found
during simulation.
Depending on the severity of the problem,
The simulator is instructed to continue
simulation or halt.

40. Assert - syntax ASSERT condition [REPORT "message“]
[SEVERITY severity_level ];
The message is written when the condition
is FALSE.
Severity_level can be:
Note, Warning, Error (default), or Failure.

41. Assert – Examples (1) assert initial_value <= max_value
report "initial value too large"
severity error;
assert packet_length /= 0
report "empty network packet received"
severity warning;
assert false
report "Initialization complete"
severity note;

42. Report - syntax REPORT "message" [SEVERITY severity_level ];
The message is always written.
Severity_level can be:
Note (default), Warning, Error, or Failure.

43. Report - Examples report "Initialization complete";
report "Current time = " & time'image(now);
report "Incorrect branch" severity error;

44. Example of Design Under Test
MUX_0 1 A1 A
MUX_4_1
IN0 Y1
MUX_1
NEG_A 1
IN1
MUX_2 Y
IN2
OUTPUT
IN3
SEL0
SEL1
NEG_Y 1 B1 B L1 L0
MUX_3
NEG_B

45. Example 1
Simple Testbench
MLU_tb.vhd

46. Developing Effective Testbenches
Part 4
Introduction to Lab 1:
Developing Effective Testbenches
ECE 448 – FPGA and ASIC Design with VHDL

47. Part 1: Verifying Combinational Logic Status Monitoring Unit
SMU
ECE 448 – FPGA and ASIC Design with VHDL

48. Interface
ECE 448 – FPGA and ASIC Design with VHDL

49. Ports (1)
ECE 448 – FPGA and ASIC Design with VHDL

50. Ports (2)
ECE 448 – FPGA and ASIC Design with VHDL

51. Discrepencies The provided Post Synthesis Simulation Model smu_psm.vhd
contains several discrepancies compared to the specification.
These discrepancies may have for example the following forms:
The functions of two outputs are swapped
A flag is high for values other than those defined in the specification
A flag is stuck at 0 or 1, etc.
ECE 448 – FPGA and ASIC Design with VHDL

52. Tasks and Deliverables
Write a testbench capable of detecting all discrepancies.
Write a short report describing all discrepancies and test vectors capable of detecting them.
Deliverables:
VHDL code of the testbench.
ISim waveforms obtained by applying your testbench (in the PDF format)
Report describing the choice of test vectors for each operation, and all discrepancies you have managed to detect.
ECE 448 – FPGA and ASIC Design with VHDL

53. Part 2: Verifying Sequential Logic Linear Feedback Shift Register
LFSR
ECE 448 – FPGA and ASIC Design with VHDL

54. Linear Feedback Shift Register LFSR
Generates a sequence of numbers that approximates the properties of random numbers
The sequence is fully deterministic, i.e., it can
be repeated based on an initial state of LFSR
The period of the sequence may be made very large (typically, 2L-1, where L is an internal state size)

55. Applications of LFSRs Random Numbers are often important
Testing of VLSI circuits
Cryptography
Monte Carlo simulations
Noise addition
Bit error detection,
and many other applications

56. Linear Feedback Shift Register (LFSR)
Each stage = D flip-flop
 L, C(D) 
Length
Connection polynomial, C(D)
C(D) = 1 + c1D + c2D cLDL

57. sj = c1sj-1  c2sj-2  . . .  cL-1sj-(L-1)  cLsj-L
Initial state
[sL-1, sL-2, , s1, s0]
LSFR recursion:
sj = c1sj-1  c2sj-2   cL-1sj-(L-1)  cLsj-L
for j  L

58. Example of LFSR  4, 1+D+D4 Length Connection polynomial, C(D)
C(D) = 1 + 1D + 0D2 + 0D3 + 1D4
c1=1
c2=0
c3=0
c4=1

59. LFSR State Sequence s4 s3 s2 s1 s0
s4 = c1s3  c2s2  c3s1  c4s0 = s3  s0

60. Block Diagram of Lab 1 LFSR
c3, c2, c1, c0 are constants
different for each Post Synthesis Model (.ngc)
c can be:
treated as std_logic_vector(3 downto 0)
a hexadecimal digit, ‘0’..’F’
ECE 448 – FPGA and ASIC Design with VHDL

61. Post Synthesis Simulation Models
In the provided four Post Synthesis Simulation Models,
1. lfsr_1_psm.vhd
2. lfsr_2_psm.vhd
3. lfsr_3_psm.vhd
4. lfsr_4_psm.vhd,
these coefficients have been set in a random order
to one of the following four values:
A. c=“0011” = X“3”
B. c=“1001” = X“9”
C. c=“1011” = X“B”
D. c=“1101” = X“D”.
ECE 448 – FPGA and ASIC Design with VHDL

62. Tasks and Deliverables
Write a testbench capable of comprehensively testing all LFSRs.
Write a short report describing your approach for matching LFSRs with the corresponding coefficient values.
Deliverables:
VHDL code of the testbench.
ISim waveforms obtained by applying your testbench (in the PDF format)
Your report, describing your approach and findings. Your report should also include a table with the expected values of LFSR states (until they start repeating) for each of the four values of c and a selected initial state of LFSR.
ECE 448 – FPGA and ASIC Design with VHDL

63. Part 5a Hands-on Session: ISim Tutorial
ECE 448 – FPGA and ASIC Design with VHDL

64. Part 5b Hands-on Session: Class Exercise
ECE 448 – FPGA and ASIC Design with VHDL