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Hyung-Ock Kim, Jun Seomun, Jaehan Jeon, Chungki Oh, Wook Kim, Kyung-Tae Do, Jung Yun Choi, Hyo-Sig Won, Kee Sup Kim Samsung Electronics, Korea.

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Presentation on theme: "Hyung-Ock Kim, Jun Seomun, Jaehan Jeon, Chungki Oh, Wook Kim, Kyung-Tae Do, Jung Yun Choi, Hyo-Sig Won, Kee Sup Kim Samsung Electronics, Korea."— Presentation transcript:

1 Hyung-Ock Kim, Jun Seomun, Jaehan Jeon, Chungki Oh, Wook Kim, Kyung-Tae Do, Jung Yun Choi, Hyo-Sig Won, Kee Sup Kim Samsung Electronics, Korea

2 Temperature, One of Design Keys in Mobile SoC Temperature-limited operation is inevitable to prevent human skin burn in mobile devices Owing to performance trends and small form factor, temperature is a crucial design criteria in mobile SoC design Thermal Management To keep a silicon below temperature limit at the cost of performance sacrificing Conventional thermal management achieved by voltage / frequency drop [1-3], i.e. thermal throttling in Figure 1, which must accompany performance drop Besides, it is required to prevent power source shutdown whenever thermal runaway happens Since leakage power has strong feedback to temperature, it is an important momentum of temperature increase in mobile SoC, which is given by [4] 1 (1) Time Temp. Vdd Thermal throttling operation Freq. Voltage, freq. drop Thermal upper limit Thermal lower limit Figure 1. Thermal throttling operation.

3 Body Bias Control [5] Figure 2 shows leakage current reduction by use of reverse body bias (RBB) in nanometer-scale technologies RBB can be utilized to relieve thermal throttling by weakening leakage-temperature feedback Advanced Thermal Design and Management by Body Bias Use We propose body bias design and optimization scheme spanning from system-level design to post silicon tuning to enhance thermal management In design stage, thermal-leakage feedback and body bias design cost are formulated so as to decide body bias use, which is followed by body bias implementation In post silicon, body bias use is explored and optimized both to optimize peak performance and to save total power The proposed scheme has been implemented in 32nm HKMG commercial mobile SoC, Exynos 4 Quad, and it results in 12.3% performance improvement in high speed mode and 19.1% total power saving 2 Figure 2. Leakage current reduction by RBB of 0.4V.

4 Overall Design and Optimization Flow In early-stage design decision, cost and gain of body bias are evaluated in a CPU core and other digital blocks (named as SoC) Once body bias use is determined, body bias circuits including body bias generators (BBG) and power management unit are integrated into design In back-end, implementation and validation of body bias network are exercised Post-silicon optimization is a body bias tuning to minimize total power and maximize peak performance respect to process variation and temperature 3 Front-end design Back-end design Silicon testSilicon Board, SW stacks Early-stage design decision Body bias design Body bias implement. Post-silicon optimization Figure 3. Design flow of advanced thermal management.

5 Body Bias Design Flow Early-stage design decision in a CPU core -Body bias comes at the cost of area: body bias generator, body bias network, and power management unit -The cost of body bias can be estimated at floorplan stage, and then decided whether body bias is accepted or not -If thermal runaway by leakage is expected to appear, we must adopt body bias not to loose performance by leakage current 4 Body bias area estimation (2) Thermal runaway estimation [4] (3) If equation (3) is not converged, thermal runaway is expected CPU Chip SoC n comes from body current calculation (will be covered later) comes from design experiences

6 Body Bias Design Flow Body current calculation to determine # BBG -Body current (GIDL and junction leakage) calculator has been developed to calculate body current, so that we can find proper number of BBG to drive a block -A proposed calculator utilizes a set of look-up tables which are pre-defined for logic and memory bit cell by using SPICE simulation -Figure 4 presents calculation flow of body current and it is compared to silicon measurement in Figure 5, which shows proposed calculator over estimates body current up to 20% -# BBG is expressed by max body current / BBG driving limit 5 Searching body currents in operating conditions Gate counts, # bit cells Process corner, Vdd, temperature, body bias Body current look-up tables Calculating total body currents with design information Body currents Design informationOperating conditions Figure 4. Body current calculator. Figure 5. Comparison of calculated and measured body current in SoC silicon.

7 Body-Bias-aware Thermal Control Figure 6 shows overall thermal management scheme utilizing body bias Thermal management unit (TMU) periodically reads out temperatures from on-chip sensors Once a temperature exceeds thermal upper limit (recall Figure 1), interrupt controller asserts thermal throttling to CPU, and then CPU controls Vdd, frequency, body bias through Vdd / freq / ABB manager Vdd / freq / ABB values for thermal management is defined in post silicon optimization, which maximize thermal relaxation efficacy and to minimize performance loss 6 Temp. sensors TMU Interrupt controller CPU Vdd / Freq / ABB manager BBG PLL Regulator Figure 6. Thermal management scheme using Vdd, frequency, and body bias control.

8 Search for Optimal Thermal Management Point Thermal management optimization can be achieved by empirical practice because it can exactly capture temperature changes by real user scenarios and real mobile sets (e.g. smartphone, tablet) Using RBB expands search space because RBB efficacy is dependent to leakage portion and Vdd compensation for slow down increases dynamic power Leakage portion is changed by process variation, DVFS control, and even ambient temperature Figure 7 presents inverter path delay increase by RBB, where 40~50mV Vdd compensation is required for 0.4V RBB This can increase engineering cost and optimization TAT in post silicon Therefore, we will use simplified RBB policies: -Use of RBB is decided for each silicon group (binning group) respect to process variation -But we will merge RBB applying condition for each silicon group if they show similar characteristics 7 Figure 7. Inverter path delay increase by RBB.

9 Exynos 4 Quad as Test Vehicle Figure 8 presents block diagram of Exynos 4 Quad, where CPU is Cortex A9-based quad cores running up to 1.4GHz -To enhance computation performance, GPU, multimedia processors and interface units are integrated along with 6.4GB/s dual-channel DRAM interface for wide memory bandwidth Body bias is used in quad core CPU to optimize thermal throttling Thermal throttling evaluation board is shown in Figure 10 Power can be measured by external multimeter, and thermal throttling and on-chip temperature are transferred to PC via RS-232-C connection on the fly 8 Figure 9. Thermal throttling evaluation board. Figure 8. Exynos 4 Quad block diagram. Video Audio File Image Camera Display CPU core L2 Cache DRAM Controller GPU 6.4GB/s dual channel Body bias domain #1Body bias domain #2

10 Thermal Optimization Practice Process variation and body bias control -The use of RBB can be manipulated respect to process variation -Figure 10 shows total power measurement in various temperatures in high performance mode -Fast silicon shows steeper total power increase over temperature owing to leakage current -As is clear, in lower temperatures, RBB use results in power increase owing to voltage compensation of 50mV; breakeven points are 65°C and 75°C in fast and slow silicon, respectively -Because typical temperature in high performance mode is over 75°C, RBB can be activated regardless of process variation 9 Figure 10. Total power saving by RBB use in (a) fast silicon and (b) slow silicon running at max speed. (a)(b) Breakeven point

11 Thermal Optimization Practice Thermal throttling improvement and total power saving -Table 1 shows thermal throttling improvement measurement by RBB use in real application setup (running OS) -Time-before throttling start is improved by up to 171.0%, which means if an application requires only short time of high performance mode, it may not experience performance loss by throttling -In real application, normal status is improved by up to 12.3% by using RBB -Figure 11 shows total power saving measurement by RBB use in 1.0GHz operation and total power saving is up to 19.1% -It is clear that RBB efficacy is getting better in high temperature and fast silicon 10 Slow siliconFast silicon Time-before throttling start improvement [%] 82.0171.0 Normal status improvement [%]7.012.3 Table 1. Performance improvement by RBB in real application setup (running at max speed) Figure 11. Total power reduction by RBB use in running at 1.0GHz. Mode transition High performance mode Thermal throttling Time-before throttling start Freq.

12 Thermal throttling has been used so as to obey thermal limit to prevent human skin burn while maximizing user experience in high performance mobile SoC We have proposed a new thermal throttling method based-on RBB, which spanning from system-level design to post-silicon optimization In system-level design, cost and efficacy of RBB use are formulated for high performance CPU Body current calculator has been developed for robust design of RBB and thermal management scheme using RBB is presented In post silicon optimization, we have proposed empirical policy to reduce engineering cost and maximize RBB efficacy to reduce thermal throttling Proposed design and optimization have been applied to commercial mobile SoC, Exynos 4 Quad in 32nm HKMG Proposed method improves peak performance by up to 12.3% in fast silicon and it can save total power up to 19.1% in 1.0GHz operation 171% improvement of time-before throttling start means proposed methodology can decrease thermal throttling chance when an application requires short period of high performance 11

13 [1] D. Brooks and M. Martonosi, Dynamic thermal management for high-performance microprocessors, in Proc. ISCA, pp. 171182, 2001. [2] K. Skadron and et al, Temperature-aware micro-architecture: modeling and implementation, ACM Transaction on Architecture and Code Optimization, Vol. 1, No. 1, pp. 94125, 2004. [3] A. Naveh and et al, Power and thermal management in the Intel Core Duo processor, Intel Technology Journal, Vol. 10, No. 2, pp. 109122, 2006. [4] J. H. Choi, A. Bansal, M. Meterelliyoz, J. Murthy, and K. Roy, Self-consistent approach to leakage power and temperature estimation to predict thermal runaway in FinFET circuits, IEEE Transaction on Computer-Aided- Design, Vol. 26, No. 11, pp. 20592068, 2007. [5] J. W. Tschanz and et al, Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage, IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 13961402, 2002. [6] D. Markovic, C. C. Wang, L. P. Alarcon, T.-T. Liu, and J. M. Rabaey, Ultralow-power design in near-threshold region, Proc. IEEE, Vol. 98, Issue 2, pp. 237-252, 2010. [7] Y. Wang and et al, A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management, in Proc. ISSCC, pp. 456457, 2009. [8] C.-H. Jan and et al, A 32nm SoC platform technology with 2 nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications, in Proc. IEDM, pp. 14, 2009. [9] S. Borkar, T. Karnik, S. Narenda, A. Keshavarzi, and V. De, Parameter variations and impact on circuits and microarchitecture, in Proc. Design Automation Conference, June 2003, pp 338342. 12

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