1. Chiche Ronic Caceres Thierry Duarte Olivier
Packing
Chiche Ronic
Caceres Thierry
Duarte Olivier
LHCb upgrade meeting

2. Data flow and firmware architecture
CROC prototype tests : schedule
Schedule for SPECS development
A3PE1500 FPGA
ADC 12 12
ADC
Packing
ADC 12
Data register
Buffer RAM
8 to 16 .
GBT
Multi-Gb/s
Data
Transmission
ADC 12 10
Formatting
ADC datas
(pipeline)
Data compression 10
Mux 12
Optical link
ADC
ADC 12
Data register
Buffer RAM
Event counter (350)
ADC 12
ADC 12
BXId and Energy calculation
Output data format :
1 byte
1 byte
1 byte
5 bytes
2 bytes
BXId
Energy
Mapping
8 Shorts ADC
2 long ADC
LHCb upgrade meeting
February 11th 2011

3. Firmware architecture and data size
CROC prototype tests : schedule
Schedule for SPECS development
(x8) ADC
Comparator 12 12 12 12 12 12 12 12
Formatting ADC datas
Comparator
Pedestal +23
BXId and Energy calculation
Short
Long
Mapping
Short (5 bit)
Pedestal -8
Shift
Long (12 bit)
BXId
1 byte
Energy
Mapping
8 Shorts ADC
5 bytes
0 to 8 bytes
long ADC
8 to 16
Packing
LHCb upgrade meeting
February 11th 2011

4. Firmware : data flow packing proposal
Event Data flow 16 15
Circular buffer (32 x 8 bits) 12
10 bytes register N
PN+1 10
RAM buffer
Formatting ADC datas PN
BXId
1 byte
Energy
Mapping
8 Shorts ADC
5 bytes
0 to 8 bytes
long ADC 8
Mux
Mux
GBT
PN-1
RAM buffer I
10 bytes register
350 Events
350 Events
? Data ? P I
State Machine
@ 80Mhz
P : Wr pointer
N : length word
I : Rd pointer
N = 8 to 16 bytes
40Mhz
80Mhz
40Mhz
LHCb upgrade meeting
February 11th 2011

5. Firmware : State Machine - Rd/Wr circular buffer - Wr RAM buffer, Rd ?
Clock state machine 80 Mhz
Clock event 40 Mhz t0
Idle
Start Acq
Rd de la longueur du mot N
Wr du mot de longueur N dans buffer circulaire
Calcul de S = P + N – I comparé à 10, 20;
Avec P : Pointeur de Wr
N : Longueur du mot Wr
I : pointeur de Rd t1
Stop Acq
S  10
10 ≤ S  20
S ≥ 20
Lecture de 2x 10 bytes du buffer circulaire
Increment (I + 20) t2 t3 t4
Lecture de 10 bytes du buffer circulaire
Increment (I + 10)
Calcul " longueur d’occupation S "
LHCb upgrade meeting
February 11th 2011

6. SPARE
LHCb upgrade meeting
December 10th 2010

7. ADC comparator to short, long
CROC prototype tests : schedule
Schedule for SPECS development
Long (12 bit) t0
Pedestal +23
Start Acq
Pedestal
Short (5 bit) t1
S = P + N – I
Stop Acq
Pedestal -8
S  10
S ≥ 20
10 ≤ S  20
Long (12 bit) t2 t3 t4
Rd 10 bytes
(I + 10)
Rd 20 bytes
(I + 20)
LHCb upgrade meeting
February 11th 2011