1. Avidan Efody, Mentor Graphics Corp.
Whose fault is it? Advanced techniques for optimizing ISO fault analysis
Avidan Efody,
Mentor Graphics Corp.
Todo :
slide about power analogy?
Slide with some real numbers (i.e. standard error and probability)
Slide with “you are here”?
FIT -> SPFM/PMHF?
Concepts used – maybe at the beginning

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Motivation
ISO requirements for fault analysis
Similar requirements from other standards
Requirements from mission-critical domains
Data center
Networking
And many more
No end-to-end how to available
2/16/2019
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3. Agenda
The problem
Solution requirements
Proposed solution

4. The problem : concept Safety concept is developed at high level
Presentation Title
The problem : concept
Safety concept is developed at high level
Failure In Time (FIT) budgets per part
Technical assumptions on IP (SEooC)
Safety mechanisms
Clk & power
RAM &ROM
Shows graphic of complete E/E system from section-5
Actuato\Sensor
? FIT
Inputs
MCU
? FIT
Bus
Other logic
? FIT
? FIT
? FIT
? FIT
Actuato\Sensor
Outputs
? FIT
? FIT
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5. The problem : element requirements
IP requirements derived from system analysis:
Contribution of element to overall FIT<10%
<10% of faults are single point/residual
Debug logic not used in safety-critical operation
Faults in debug logic are safe
More…

6. The problem: typical flow
Presentation Title
The problem: typical flow
Once implementation is in place its FIT must be accurately measured
Bridging
Transient
Logical/
Sequential de-rating
Timing de-rating
Use case de-rating
whatisthisslide – elephant in the hole
Explain what is required from a fault analysis engine at RTL/Gate – fault models, quick results, optimizations, who can do it (us or partners)
Stuck-at
D.C
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7. The problem: FIT doesn’t fit
Presentation Title
The problem: FIT doesn’t fit
What if FIT doesn’t fit?
Iterations are expensive
Re-plan, re-design, re-verify
Schedule delays
Graphics : Poo stuck in the hole
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8. Solution requirements
Accuracy/cost trade-off
Statistical strength
Integrated with overall verification
Seamless abstraction switch
Multi-platform

9. Proposed solution Statistical sampling of faults Population
Sample size
Fault points
Analysis
Traditional method
Avoiding reruns
Avoiding diff/duplication
Multi platform
Probabilistic metric

10. Population = test X cycle X signal? Good enough: But: Rigorous RBV
Presentation Title
Population
= test X cycle X signal?
Good enough:
Rigorous RBV
Interesting states covered
Biased to corner cases
But:
Fault analysis leads to more stimuli requirements
Assume fault in given state doesn’t produce any impact, does this mean anything?
This is statistical analysis, we’re not covering many faults anyhow
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11. Sample size Variance ∝ 1/ 𝑁 Sanity check: ∝ De-rating factor
Presentation Title
Sample size
Variance ∝ 1/ 𝑁
Brute force method
Sanity check:
∝ De-rating factor
Let some faults -> Failures
Final analysis:
∝ required accuracy
High level trade-off
Analysis cost <> design cost
≈ ∞
Assume fault in given state doesn’t produce any impact, does this mean anything?
This is statistical analysis, we’re not covering many faults anyhow
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Fault points 52 48
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Fault points
Smaller variance -> cheaper analysis
Segmentation of population helps 80 70 20 30
Jewish
Asian-American
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14. Fault points Transient faults Makes sense to separate
Presentation Title
Fault points
Transient faults
SET – in logic
SEU – in memory
Makes sense to separate
SET de-rating is lot higher
Also, cell FIT ratio different
FF/Mem FIT rate higher
Separate statistics
Smaller variance
Smaller cost
Signals fault probability varies
Gate vs. FF vs. Memory
Crude approximation:
Gate 1, FF 4, Memory ∝ cells
Refined approximation
FIT per cell from fab
Faults per type by weighted avg
High level take-away
Better correlation -> less analysis
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15. Analysis : Traditional flow
Presentation Title
Analysis : Traditional flow
Run reference test
Rerun test with fault
Diff safety critical
How can we optimize that?
Slide with fault types from TVS - classification
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16. Analysis : Minimize scope
Time scope:
Fault time -> 0
Design Scope:
∩ between:
Fault point fan-out
Safety critical fan-in
Stimuli
Initialize FFs, Mems
Scope inputs forced 2 1
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17. Analysis: Minimize compare
RTL simulators already have a way to capture undefined state…
Good tool support
Attention to X optimism/pessimism (at RTL)
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Analysis: decision
T=0
T=10 => MPF 2 2 1
T=10 => SPF or RF
T=End => USER 2 2 X 1 X
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19. Analysis : abstraction
RTL or structural gate?
SET
Structural gate to 1st FF
RTL from there
SEU
RTL all the way
Requires RTL->GL flop mapping
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20. Analysis: multi platform
Emulation/prototypes can fit in flow if:
Results can be reproduced
FFs/Memories can be dumped
Signals into scope can be logged
Combine platforms strengths
Emulation/prototyping for long runs
Simulation for X injection
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PMHF
Example, assume no SM
Outputs of above:
SEU SPF rate +/-
SET SPF rate +/-
PMHF:
(SPF RATE) * (# of FF) * (FF FIT) + …
Probability of PMHF < Target
Target – PMHF >= 5σ =>
Target – PMHF >= 7σ =>
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Summary
Fault simulation is an interesting challenge
There’s more than just diff to it
Requires upfront consideration/planning
And an end-to-end flow
Hopefully this paper will help…
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Thanks
2/16/2019
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