1. CMOS Technology Flow varies with process types & company
N-Well CMOS
Twin-Well CMOS
STI
Start with substrate selection
Type: n or p
Doping level, →resistivity
Orientation, 100, or 101, etc
Other parameters

2. N-well CMOS (ON.5um) pMOS transistors in n-well
nMOS transistors on substrate
nMOS transistor’s body is always connected to lowest voltage of chip
nMOS is a three terminal device
pMOS body can be tied to voltages other than Vdd
pMOS is a four terminal device
0.35um and larger typically n-well

3. VDD M2
Vin Vo M1

4. Relative size of different layers

5. Deep SubMicron Challenges
Transistor sizes become very small
But FOX lateral size cannot be reduced
Depletion region between p-well and n-well not reduced
Large area
FOX
depletion

7. Shallow Trench Isolation Technology
Allowing transistors to be spaced closer

8. Devices available Transistors and wires
Deep wells good for substrate noise isolation

9. Resistors Diffused and/or implanted resistors. Well resistors.
Polysilicon resistors.
Metal resistors.
Thin film resistors

10. capacitors In older processes, you put the bottom plate on FOX
Junction capacitors
Gate capacitors
Poly-poly capacitors
Metal-metal capacitors
In older processes, you put the bottom plate on FOX

11. Metal-metal capacitors
Very linear cap
More expensive to make

12. Inductors

13. Sub 100nm CMOS Technology State of the art is 14 nm
45 nm is in wide use for high speed
65 nm also in wide use for SoCs
Grad students in our group have access to certain 28nm, 45 nm, 65 nm, 130nm, 180nm, 0.5mm technologies
Have designed in such technologies
But analog transistors use L = 0.6, 0.9 mm

14. HW Go to the MOSIS webpage Find and download the NDA for IBM0.13
Sign it, either give to TA in person, or scan and to TA

15. Advantages Digital Viewpoint: Analog Viewpoint: Improved Ion/Ioff
Reduced gate capacitance
Higher drive current capability
Reduced interconnect density
Reduction of active power
Analog Viewpoint:
More levels of metal
Higher fT
Higher capacitance density
Reduced junction capacitance per gm

16. Disadvantages for analog
Reduction in power supply resulting in reduced headroom and signal power
Gate leakage currents
Reduced small-signal intrinsic gains
Increased nonlinearity (IIP3)
Noise and matching??
Reduced signal to noise ratio
Anne-Johan Annema, et. Al., “Analog Circuits in Ultra-Deep-Submicron CMOS,” IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp

17. the Gate Leakage Problem