Presentation on theme: "EML 4561 Introduction to Electronic Packaging"— Presentation transcript:
1 EML 4561 Introduction to Electronic Packaging W. Kinzy Jones, Professor MMEMWF 11:00-11:50(mobile)(office)
2 Notes on the fieldI am Past President and Fellow, IMAPS, The Microelectronics and Packaging SocietyResearch in advanced packaging, 1st Level Assembly, Thermal Management, Components and Electronic Materials- Funded over $7MM in past 15 yearsElectronic packaging is a application field that crosses over many disciplines. There are 80,000 ME working in the field. Conferences/journals by ASME, IEEE, ASM, IMAPS, etc.All former graduate student hired prior to graduation!
13 Trend to Convergent Systems Transistors / chipWW S/C Revenue ($B)10000All businesses, people, objectsNetwork computingWide area / bandwidthGraphical, voice, multimedia, etc.Many vendors / platforms100B10B10001BPCs / ServersWirelessWiredInternet100M10010MMainframesBusinesses & some peopleClient-server computingLocal area connectionText/graphical interfaceMany vendors / few architectures1M10PCs100KBusinessesHost-based computingMainframeDumb terminalFew vendors / architecture10K11K197519952015TodaySource: Russ Lange, IBM MicroelectronicsYear
14 What are Convergent Microminiaturized Microsystems (CMM)? Convergent: Two or more functionsMicrominiaturized: >1000x volume reductionsMicrosystems: systems with micro-scale technologies
15 Trend to Convergent Microminiaturized Systems (CMM) FunctionalData and VoiceVideoCell PhoneCONSUMERELECTRONICSMedical Implant/Diagnostic Monitor/ CommunicatorMEDICALTechnologyDigital, RF, Analog and OpticalProductComputer, consumer and telecom
19 SOC Challenges Integration RF Limits Fundamental Digital Limits Major Delay ProblemsSummaryFundamentalDesign & Verification ComplexityTest ComplexityProcess ComplexityMixed Function CostsWafer Fab CostsLegal ProblemsTime-to-market
20 SOC: Integration of Two or More Mixed Functions in a Single IC (b)
21 What is Wrong with Current Packaging for Tomorrow’s Needs? Higher CostBulky SizeCellular PhoneWeight TrendActive ICs 10%Passives: 90%Lower PerformancePoorer ReliabilityIC: PPBSystems Pkg: PPMBarrier to all future systems
22 What is SOP, SIP, or Board? A.) Today’s Board: Interconnect Components RF ICDigital ICOptical ICSubstrateA.) Today’s Board: Interconnect ComponentsFlashRAMmPICPackageSuper IC Stack (ASET)Package (Fujitsu)Stacked IC (Amkor)B.) SIP: Stacked Chip/Package for Reduced Form Factors3-D ICsICRF ICOpto ICDigital ICRFOptoElectricalPackage with Opto, RF, Digital FunctionsC.) SOP: Optimizes Functions Between ICs and Package
23 What are SOC, SIP, and SOP? SOC: System on Chip SIP: System in Package Highly integrated and mixed signal IC with partial system functions in one componentSIP: System in Package3-D IC or Package AssemblyRequires Systems BoardSOP: System on PackageMicrominiaturized system-level board with two or more embedded RF, digital, analog and optical functionsBest of on-chip and package integration for cost, performance, size and reliabilitySimilar to SOC but total system function in a microminiaturized board
24 SOP: SIP + SOC+Systems Board 3 -D Stacking of ICS or Package Structures, Similar to PWBMacro dimensionsVertical stack upTestable3 -D Build up, similar to IC FabricationMicro to Nano dimensionsSequential build up and test similar to MCM-D and ICWafer to IC concept for high yieldMEMSGa-AsSIPSOCSOCMEMSGa-AsSIP
25 Why SOP?SOC is complex to design and test, expensive to Fabricate, long time-to-market and presents fundamental limits.IC company’s dream for decades. No complete system has been shipped to date.SOP optimizes the best of IC and package integration for cost, performance, size and reliability.Faster turn-around and faster time-to-market.Provides full system solution today that SOC provides tomorrow.SIP is a 3-D IC or package, not a complete system
26 Information Technology is a Trillion $ Industry Microsystems & Packaging is 25% of IT Industrial &Medical11%$105BAutomotive5%$ 48BMilitary9%$ 8.7BConsumer26%$112BBusiness Equip38%$ 383BCommunications26%$ 259BSource: Prismark
27 MSP Market ($320 B) Opto & MEMS ($30B) Microelectronics ($165B) Systems Packaging ($125B)
28 Information Technology and Microsystem Markets Billion $/Year
54 Solder Primary functions Electrical connection between component and interconnectMechanical attachment of component to boardThermal path from component to boardAlloys of various compositions and melting pointsLead-Tin solder most commonEutectic composition: 63% Tin, 47% Lead60/40 or 2% silver addedSolder paste for screen printing, pressure dispensingAlloy particlesFlux and activator chemicalsVehicle to control viscosityWave solderingFoam or spray fluxPreheat boardTurbulent wave to spread solderLaminar wave to smooth
55 Effect of Underfill on Temp Cycling Performance With filler, 27ppm
60 Packaging Considerations that Effect the Electrical Performance
61 Interconnects Worsen: Signal IntegrityPerformance: switching, speedReliabilityForm, fit, and function- weight, volume, power
62 Interconnects Can Have Very Important Electrical Properties PropertySelf-inductanceCapacitance to groundtransmission lineMutual Inductance, capacitanceResistance, lossPossible ImpactGround bounceDelay, power sagPropagation delay, reflectionCross-talk, noiseDamping, ringing, power sag
63 Drivers for Reduction of Interconnect Length Directly reduces inductance, capacitance, resistance and delayIndirectly reduces switching time, power, size, ringing, ground bounce, and power sag
64 Electrical Fundamentals Resistance ( ohms). Relates Ohms law relationship between current and voltage, V=IR. Resistivity, , is a materials property, in ohm-meters. Resistance, R = Length x / cross-sectional area of conductorCapacitance (farads) relates to the ability to store charge. Capacitance for a parallel plate capacitor is proportional to the dielectric constant,K, times the area of the plate/ thickness of dielectric.Inductance ( henry)- relates to the voltage generated to oppose a change in current
65 Basic Resistance Equation Resistance R = L / A = L /wt = L/w Rs where Rs is defined as the sheet resistivity, is resistivity, L is the length and A is the cross sectional area of the conductor/resistorA square ( L=W ) for a fixed thickness of material has a fixed resistance per square, independent of size. A square anything
66 Capacitance is In the insulation between more than one conductor Orders of Magnitude higher outside the chip than insideThe dominate determinant of digital speed
68 Capacitance of Electrically Short Interconnections Capacitance is the sum of all output capacitance of all drivers to that interconnect, the input capacitance of all receivers, and the distributed capacitance to ground of the interconnection
69 Switching Time, PowerIf a step voltage is applied to an RC network, the time delay is proportional to RC. If the capacitor is charged from zero to full charge, the energy dissipated, W, is independent of R and equals CV2/2. But energy is also power X time delay. If we operate twice as fast, the circuit will dissipate twice the power.
70 InductanceOpposes a change in current by generating a back voltage. If the current change is positive, the back voltage subtracts from the voltage applied, causing a power sag.The voltage is equal to the inductance times the rate of change of the current , VL= L di/dtSelf inductance exists in every wire, trace, wire bond, solder joint, etc..It is minimized by large, short conductors, or a sheet conductor as a ground or power plane.Example: If we switch 1 amp in 5 nsec on a 1” trace with 7.8 nH, we generate a back voltage of 1.6 volts.
71 CrosstalkThere is a mutual capacitance between two adjacent insulated conductors that couples a fraction of one voltage to the otherThere is also mutual inductance, functioning as a transformer by generating a voltage in each when the current changes in the other.This is crosstalk. Can be minimized by design (keep talkers and listeners apart) and use of ground/power traces between talkers/listeners
72 Ground Bounce, Power Sag Cause: Common-mode impedance, usually inductiveDigital devices require most of their power supply current during switching. Clocked signals switch together, so there could be a large total surgeThe inductance in the power and ground leads causes ground bounce and power sag.
73 Bypass ( decoupling) Capacitors To reduce power sag and ground bounce, add decoupling capacitors. Value should be nF/sq.cm of silicon. Decoupling capacitors should have low parasitic inductance.Capacitors serve as local energy reserves and need to be close to the power/ground leads
74 RLC Circuit SwitchingThe voltage step sent down an interconnect can be distorted badly by the R, C, and L on the interconnectThis distortion can be removed by the right balance of the values of R,L and C. When R = 2* sqrt(L/C), critical damping occursIf R is above critical damping, switching slows down; if below, ringing of the signal occurs
76 Transmission LinesAny interconnect whose length is over a small fraction of the wavelength of the signal it carries acts like both a transmission line and an antenna radiating or receiving noiseAs speed increase, the lumped analysis of L,R,and C components must be replaced by the distributed network of L,R, and C.Property shielded interconnects minimize the effect of antenna properties, but the transmission properties remain
77 Transmission Line Properties A transmission line appears as a string of small inductors and capacitors, with seven principal properties:length L, inductance per unit length, capacitance per unit length, impedance (Z), attenuation, propagation velocity, and time delay
79 Transmission line traces Matched impedance systems require containment of the electrical fields. This has lead to designs including the stripline, the microstrip, the buried microstrip. Additionally, for multilayer routing, vias must be consideredStripline microstrip
81 Traveling Waves on an Infinite Line Switching on a DC source voltage, V, :draws the same current as a resistor of value Zo connected to V.current flows down the line at the propagation velocity, while the current progressively charges up the line capacitance to voltage V. Hence a voltage step V also travels down the line.Draws current indefinitely due to an infinitely long lineThe source only sees a resistive load Zo continuously drawing current
82 Traveling Waves on an Unterminated Line When the line is unterminated ( R is infinite):Kirchoff’s current law still applies at the far end: the sum of current entering the end must equal the current leaving the end. But there is no load to draw current from the end node.Therefore, an equal reflected current wave is generated that travels back toward the source.This reflected current wave requires an extra voltage source, V, to propel it, so the voltage at the far end steps up to 2V.This increased voltage travels back towards the source along with the reflected current.What happens at the source depends on the source’s internal impedanceThe waves can on occasion reflected back and forth several times
83 Lines Traveling Waves Capacitively Terminated The problem of reflection is compounded by capacitance at the ends.When a transmission line drives a capacitor, the extra capacitance causes:reflections, since the line is now mismatchedringing for some drivers, since there is no longer critical dampingCMOS inputs are essentially capacitive.
84 AC TerminationTo minimize power dissipation, a series capacitor,C, can be added to the terminating resistorThis terminated the line only when a voltage transition occurs and allows no DC power dissipation in RThe value of C must be selected carefully, either by simulation or experimentation to minimize the effect of capacitively terminated lines.
85 When Interconnections are Electrically Significant When interconnects degrade switching timeWhen the signals are not correctly dampedWhen large amounts of current switchIn the time domain, when the line propagation delay approaches the driver switching time. Propagation delay is proportional to lengthIn the frequency domain, when the wavelength of the signal ( including harmonics) are not long compared to the length of the interconnect ( for 100 Mhz- over a few centimeters)
86 Packaging What packaging provides: InterconnectionPower DistributionThermal ManagementEnvironmental ProtectionWhat the package is made from--materials, partsWhat is used to design and fabricate packages:Facilities and EquipmentManufacturing and Design ToolsProcess by which the package is produced over time
87 Technology DrivesIncreases in semiconductor complexity from decreased feature sizeCorresponding increases in systems speedIncrease in input/output (I/O) densityIncrease in power density (W/cm2)
88 Levels of Packaging 1st Level Connection 2nd Level Connection IC to Common Circuit BaseWirebonds or solder bumps to package base2nd Level ConnectionCommon Circuit Base to Circuit BoardPackage leads soldered to PCB3rd Level ConnectionAssembly of multiple boards into larger assemblyVideo card, modem, game port on a PC motherboard4th and 5th Level ConnectionsSystem level assembly with several 3rd Level subassembliesMotion control, visual alignment, user interface, etc. in manufacturing equipment