1. Enrico Fermi Institute and Physics Dept
Why Simulation is Necessary for The Development of Large-Area Psec-Resolution TOF Systems
Henry Frisch
Enrico Fermi Institute and Physics Dept
University of Chicago
With Harold Sanders, and Fukun Tang (EFI-EDG) Karen Byrum and Gary Drake (ANL); Tim Credo (IMSA, now Harvard), Shreyas Bhat, and David Yu (students)
1/17/2019
HJF Simulation Workshop

2. Why is simulation essential?
Want maximum performance without trial-and-error optimization (time, cost, performance)
At these speeds (~1 psec) cannot probe electronics (for many reasons!)
Want optimized MCP/Photodetector design- complex problem in electrostatics, fast circuits, surface physics, ….
Debugging is impossible any other way.
1/17/2019
HJF Simulation Workshop

3. HJF Simulation Workshop
First-outline of plan for TOF at ~< 1 psec resolution for relativistic particles:
Typical path lengths for light and electrons are set by physical dimensions of the light collection and amplifying device.
These are now on the order of an inch. One inch is 100 psec. That’s what we measure- no surprise! (pictures swiped from T. Credo talk at Workshop)
1/17/2019
HJF Simulation Workshop

4. MCP’s have path lengths <<1 psec:
Micro-photograph of Burle 25 micron tube- Greg Sellberg (Fermilab)
Can buy MCP’s with 6-10 micron pore diameters
1/17/2019
HJF Simulation Workshop

5. Use Cherenkov light - fast
Generating the signal
Use Cherenkov light - fast
A 2” x 2” MCP- actual thickness ~3/4”
e.g. Burle (Photonis) with mods per our work
1/17/2019
HJF Simulation Workshop

6. Geometry for a Collider Detector
2” by 2” MCP’s
Beam Axis
Coil
“r” is expensive- need a thin segmented detector
1/17/2019
HJF Simulation Workshop

7. A real CDF event- r-phi view
Key idea- fit t0 (start) from all tracks
1/17/2019
HJF Simulation Workshop

8. HJF Simulation Workshop
Anode Structure
RF Transmission Lines
Summing smaller anode pads into 1” by 1” readout pixels
An equal time sum- make transmission lines equal propagation times
Work on leading edge- ringing not a problem for this fine segmentation
1/17/2019
HJF Simulation Workshop

9. Tim’s Equal-Time Collector
4 Outputs- each to a TDC chip (ASIC)
Chip to have < 1psec resolution(!)
-we are doing this in the EDG (Harold, Tang).
Equal-time transmission-line traces to output pin
1/17/2019
HJF Simulation Workshop

10. Anode Return Path Problem
1/17/2019
HJF Simulation Workshop

11. Capacitive Return Path
1/17/2019
HJF Simulation Workshop

12. Solving the return-path problem
0.250
0.160
0.070
2 in.

13. Mounting electronics on back of MCP- matching
Conducting Epoxy- machine deposited by Greg Sellberg (Fermilab)
dum
1/17/2019
HJF Simulation Workshop

14. End-to-End Simulation Result
Output at anode from simulation of 10 particles going through fused quartz window- T. Credo, R. Schroll
Jitter on leading edge 0.86 psec
1/17/2019
HJF Simulation Workshop

15. EDG’s Unique Capabilities - Harold’s Design for Readout
Each module has 5 chips- 4 TDC chips (one per quadrant) and a DAQ `mother’ chip.
Problems are stability, calibration, rel. phase, noise.
Both chips are underway
dum
1/17/2019
HJF Simulation Workshop

16. Simulation of Circuits (Tang)
dum
1/17/2019
HJF Simulation Workshop

17. Readout with sub-psec resolution:
Tang’s Time Stretcher- 4 chips/2x2in module
1/4
Tang Slide
“Zero”-walk Disc.
Stretcher
Driver
11-bit Counter
Receiver
PMT
CK5Ghz
2 Ghz PLL
REF_CLK
Front-end chip
1/17/2019
HJF Simulation Workshop

18. Diagram of Phase-Locked Loop
Tang Slide CP
Fref I1 Uc PD
VCO F0 LF I2 1N
PD: Phase Detector
CP: Charge Pump
LF: Loop Filter
VCO: Voltage Controlled Oscillator
1/17/2019
HJF Simulation Workshop

19. 2-GHz BiCMOS VCO Schematic
Tang Slide
2-GHz BiCMOS VCO Schematic
Negative Resistance and Current-Limited Voltage Control Oscillator with Accumulating PMOS Varicap and 50W Line Drivers
1/17/2019
HJF Simulation Workshop

20. Virtuoso XL Layout View
Tang Slide
1/17/2019
HJF Simulation Workshop

21. Phase Noise ( 3 model cases @ 27C)
@100KHz offset
Worst
Tang Slide
Best
dBc/Hz
Typical
dBc/Hz
Worst
dBc/Hz
Typical
Best
Tang Slide
Temperature: 27C
Supply: VDD=2.5V
1/17/2019
HJF Simulation Workshop

22. Transit Analysis: Comparison of Schematic and Post Layout Simulations
loads
Schematic
Post Layout
1/17/2019
HJF Simulation Workshop
Tang Slide

23. Simulation for Coil Showering and various PMTs (Shreyas Bhat)
Right now, we have a simulation using GEANT4, ROOT, connected by a python script
GEANT4: pi+ enters solenoid, e- showers
ROOT: MCP simulation - get position, time of arrival of charge at anode pads
Both parts are approximations
Could we make this less home-brew and more modular?
Could we use GATE (Geant4 Application for Tomographic Emission) to simplify present and future modifications?
Working with Prof. Chin-tu Chen and students, UCHospitals Radiology- they know GATE very well, use it regularly
1/17/2019
HJF Simulation Workshop

24. HJF Simulation Workshop
DAQ Chip- 1/module
Jakob Van Santen implemented the DAQ chip functionality in an Altera FPGA- tool-rich environment allowed simulation of the functionality and VHDL output before chip construction (Senior Thesis project in Physics)
Will be designed in IBM process (we think) at Argonne by Gary Drake and co.
Again, simulation means one doesn’t have to do trial-and-error.
1/17/2019
HJF Simulation Workshop

25. HJF Simulation Workshop
Shreyas Bhat slide
π+ Generation, Coil
Showering
GEANT4
Input Source code, Macros Files
Geometry
Materials
Particle:
Type
Energy
Initial Positions, Momentum
Physics processes
Verbose level
Have position,
time, momentum,
kinetic energy of
each particle for each step
(including upon entrance to PMT)
Need to redo geometry (local approx.➔ cylinder)
Need to redo field
Need to connect two modules (python script in place for older simulation)
PMT/MCP
GEANT4 - swappable
Pure GEANT4
Get position, time
1/17/2019
HJF Simulation Workshop

26. default “digitization” module
Shreyas Bhat slide
π+ Generation
GATE
Input Macros Files - precompiled source
Geometry
Materials
Particle:
Type
Energy
Initial Positions, Momentum
Verbose level
Physics processes
macros file
Solenoid Showering
GATE
But, we need to write
Source code for
Magnetic Field, recompile
PMT/MCP
GATE - swap with
default “digitization”
module
GATE
Get position, time
1/17/2019
HJF Simulation Workshop

27. Interface to Other Simulation Tools
ASCII files: Waveform time-value pair
ASCII files: Waveform time-value pair
Tube Output Signals from Simulation
Cadence Virtuoso Analog Environment Or
Cadence Virtuoso AMS Environment
System Simulation Results
Tube Output Signals from Scope
Spectre Netlist
Spectre Netlist (Cadence Spice)
Spectre Library
Custom Chip Schematic
IBM 8HP PDK
1/17/2019
HJF Simulation Workshop
Cadence Simulator

28. Questions-Tasks (for discussion)
Framework- what is the modern CS approach?
Listing the modules- is there an architype set of modules?
Do we have any of these modules at present?
Can we specify the interfaces between modules- info and formats?
Do we have any of these interfaces at present?
Does it make sense to do Medical Imaging and HEP in one framework?
Are there existing simulations for MCP’s?
1/17/2019
HJF Simulation Workshop