1. Research Status of Equivalence Checking at Zhejiang University
Feijun Zheng, Yanling Weng,
Jun Yang and Yongjiang Lu
Advisor: Xiaolang Yan

2. Outline Introduction Equivalence Checking Framework
Verification-oriented Synthesis
Compare-point Mapping
Combinational Equivalence Checking
Conclusion

3. Introduction Formal Verification (FV) Equivalence Checking (EC)
Increasingly used in IC verificaion
FV guarantees full verification
Three major areas are Model Checking, Theorem Proving
and Equivalence Checking
Equivalence Checking (EC)
Prove that the specification model (spec) and its
implementation (imp) have the same functionality
The problem is NP-Complete

4. Introduction Miter Circuit for equivalence checking Main Engines
Merge Corresponding PI and xor corresponding PO as
miter output
Check if all miter outputs are the stuck-at-0 case
Main Engines
BDD (Binary Decision Diagram)
SAT (Boolean Satisfiability)
Other: ATPG, BMDD, BED etc.
Cspec
Cimp
Miter Output PI O1
xor
Stuck-at-0 ? O2

5. Equivalence Checking Framework

6. Verification-oriented Synthesis

7. Verification-oriented Synthesis
Mainly based on public release of Icarus.
Support Verilog Module, UDP, Task and Function … etc
Increase the similarity between spec and imp
during synthesis and make verification easier

8. Verification-oriented Synthesis

9. Synthesis effect comparison
Multiplier Verification: spec from Design Compiler, imp from
Our synthesis system and formality
Environment: Sun Ultra-sparc60 workstation,2 CPU, 2G Memory

10. Compare Point Mapping

11. Compare Point Mapping Traditional State Space Traversal based Method
State space explosion
Using CEC to verify Sequential Design
Step 1: Find a mapping between latches in the spec and
imp design
Step 2: The circuits are cut at the latches. that is, the input of a latch will become  a PO and the output of a latch will
become a PI

12. Compare Point Mapping Problem( also called latch mapping)
Given two sequential circuits, assume two circuits have the same number of latches N. The problem is to find N latch-pairs such that each pair consists of one latch from each circuit and the two latches are combinationally equivalent .
Mapping Methods
Non-function-based: Naming, Structural Comparison
Function-based:
1) exact methods based on fixed-point computation
2) compare point partition using inequivalence information

13. Compare Point Mapping Random Simulation Partial BDD
Simulate random patterns, then do partition
depending on simulation response
Latch outputs in the same partition will assign the same value
Partial BDD
Build BDD for next-state functions ( Latch inputs)
Assume Latch outputs as pseudo PI
To avoid memory explosion： Set some PI or
Latch outputs as constant 0(or 1)

14. Compare Point Mapping Target Simulation Speed-up Point
Assume and then Verify Strategy
Effective for solving hard case
Time Consuming
Speed-up Point
Quick Sort according to partition size
Limit Targeted Partition Size
Reuse inequivalence information
Collaborate with BDD methods

15. Compare Point Mapping

16. Experiment Results Circuit Gates Latch Num s832 1734 10 s1423 2991 148
2256 12
s1494
2266
s5378
9453
328
s9234
18260
422
s13207
27571
1338
s15850
32152
1194
s35932
88795
3454
s38417
74176
3272
s38584
74460
2904
ISCAS 89 benchmark
Compare with ATPG method [Demos Anastasakis, DAC02]
Without use any non-function based methods in the experiment

17. CPU Time Comparison

18. Mapping Accuracy Comparison

19. Combinational Equivalence Checking

20. Combinational Equivalence Checking

21. Output Grouping
Different output’s logic cones may share many internal gates
Group some outputs and verify them in a single run
Dynamic output grouping heuristic based on output complex degree and sharing degree

22. SAT Engine UCSB’s C-SAT has superiority for Circuit-SAT Problem
Constrain Search Space in the selected group outputs cone
Sharing Pre-Learned Gates when solving each sub- problem
Learn from BDD Engine and C-SAT Engine
Filtering according to clause size and gate possession

23. Experiment Results Circuit Gates C-SAT+ no Grouping (sec)
C-SAT+ Grouping All (sec)
C-SAT+ Output Grouping (sec)
C5315
9357
2.02
0.21
0.22
C6288
14102
16.83
0.60
C7552
14306
2.96
0.74
0.75 C1
35037
470.05
209.21 C2
51551
795.52
290.64

24. BDD Engine Independent heuristic for selecting cut-points
Eliminate the dependency between the
cut-points as much as possible
Choose Cut-frontier with less dependency remaining
Construct Smaller BDD
Reduce the possibility of false negative

25. Conclusion We have …. As Future work ….
Develop a equivalence checking system
Support Verification between R-R, G-G, R-G
Compare point mapping Engine
Combinational Equivalence Checking Technique
As Future work ….
Support Sequential Equivalence Checking with complex design like retimed circuits etc
A Smart Way to invoke BDD and SAT Engine
Support Transistor Level Equivalence Checking

26. The End
Thank you!