# Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.1 One Hot State Machine vs Binary/Gray Code State Machine Danny Mok Altera.

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Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.1 One Hot State Machine vs Binary/Gray Code State Machine Danny Mok Altera HK FAE (dmok@altera.com)

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.2 One Hot State Machine What is One Hot –each state within the State Machine is represent by ONE BIT e.g. Four State Machine : state0, state1, state2, state3 can be represented by –4 bits : 1000 0100 0010 0001 (One Hot) One Hot State Machine –mainly gives us performance –but it consume more logic

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.3 Binary State Machine What is Binary State Machine –each state within the State Machine is encode by bits e.g. Four State Machine : state0, state1, state2, state3 can be represented by –2 bits : 00 01 10 11 (Binary) Binary State Machine –mainly consume less logic –but the performance usually is slower –can be more than one bit change from state to state (01 -> 10) both bits changed

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.4 Gray Code State Machine What is Grey Code State Machine –each state within the State Machine is encode by bits e.g. Four State Machine : state0, state1, state2, state3 can be represented by –2 bits : 00 01 11 10 (Grey Code) Gray Code State Machine –mainly consume less logic –but the performance usually is slower –ONLY one bit change from state to state (01 -> 11) one bit changed

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.5 Default in Max+Plus II In Max+Plus II, the State Machine will be coding as –AHDL/VHDL Input One Hot for FLEX (no option to turn on or off) –because FLEX having a lot of LC(DFF) –so LC is not a problem –most likely is performance problem Binary Encoding for MAX (option to change to One Hot) –because MAX having limited MC (DFF) –so MC is a problem –most likely the performance is not a problem

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.7 AHDL Example subdesign state_machine ( clk, rst, go : input; q : output;) variable hold_bg:MACHINE OF BITS (hh[1..0]) WITH STATES(h0,h1,h2,h3); begin hold_bg.clk = CLK; hold_bg.reset = RST; hold_bg.ena = VCC; case hold_bg is when h0 => if (go) then hold_bg = h1; else hold_bg = h0; end if; when h1 => hold_bg = h2; when h2 => hold_bg = h3; when h3 => hold_bg = h0; end case; q = (hold_bg == h1); end;

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.12 Altera Max+Plus II VHDL Compiler MAX the State Machine can be –BINARY CODING –ONE HOT FLEX the State Machine always –ONE HOT (no option to select) There is no option to direct Max+Plus II to do One Hot Coding in FLEX under Altera Max+Plus II VHDL Compiler

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.13 Solution Work around solution –use 3rd compiler to generate EDIF Binary, Gray Code, One Hot or Random –import the EDIF to Max+Plus II –now Max+Plus II doesnt know it is State Machine, then it will do what EDIF is

Copyright © 1997 Altera Corporation download from: www.pld.com.cn 2014-6-3 P.14 Sample State Machine library ieee; use ieee.std_logic_1164.all; package your_own_type is type t_state is (idle,state0,state01,state011, state0110,state01101, state011011, dummy0, dummy1, dummy2, dummy3, dummy4, dummy5, dummy6, dummy7, dummy8, dummy9, dummy10); end your_own_type; library ieee; use ieee.std_logic_1164.all; use work.your_own_type.all; Entity stmh is port (clk, serial_in, reset : in std_logic; match : out std_logic); end stmh; architecture body_stmh of stmh is signal present_state : t_state; begin process(clk,serial_in, present_state) begin if (reset = '1') then present_state <= idle; elsif (clk'event and clk='1') then case present_state is when idle => if (serial_in = '0') then present_state <= state0; else present_state <= idle; end if; when state0 => if (serial_in = '1') then present_state <= state01; else present_state <= idle; end if; when state01 => if (serial_in = '1') then present_state <= state011; else present_state <= idle; end if; when state011 => if (serial_in = '0') then present_state <= state0110; else present_state <= idle; end if; when state0110 => if (serial_in = '1') then present_state <= state01101; else present_state <= idle; end if; when state01101 => if (serial_in = '1') then present_state <= state011011; else present_state <= idle; end if; when state011011 => present_state <= dummy0; when dummy0 => present_state <= dummy1; when dummy1 => present_state <= dummy2; when dummy2 => present_state <= dummy3; when dummy3 => present_state <= dummy4; when dummy4 => present_state <= dummy5; when dummy5 => present_state <= dummy6; when dummy6 => present_state <= dummy7; when dummy7 => present_state <= dummy8; when dummy8 => present_state <= dummy9; when dummy9 => present_state <= dummy10; when dummy10 => present_state <= idle; when others => present_state <= idle; end case; end if; end process; process(present_state) begin if (present_state = state011011) then match <= '1'; else match <= '0'; end if; end process; end body_stmh;