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DoorModule and Badge 8051 RF RF XS40 FPGA 8051 XS40 (sonar) AUTH ECHO

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Presentation on theme: "DoorModule and Badge 8051 RF RF XS40 FPGA 8051 XS40 (sonar) AUTH ECHO"— Presentation transcript:

1 DoorModule and Badge 8051 RF RF XS40 FPGA 8051 XS40 (sonar) AUTH ECHO
RS232 RF BADGEID FPGA 8051 RS232 REQUEST BUSY 8051 EX1 EX0 XS40 ECHO INIT (sonar) AUTH

2 State Diagram of DoorModule
Detected user in a range of 6 inches to 3 feet within 0.5 second Detecting User Done Checking Time out in ID request Requesting ID Checking ID Timeout = worst case: 8 * 0.32s ID received

3 Detecting User: SonarTask
start SEND_INIT INIT = 1 DONE RF_TASK And FPGA_TASK WAIT_ECHO distance++ ECHO distance > MAX RESET INIT = 0 distance = 0 Time = 0.2 second/cycle 0.1ms counter => Error: +/- 0.1 ms = ft

4 Same for Both the DoorModule and the Badge:
RF Hardware Same for Both the DoorModule and the Badge: Virtual Wire Dev. Kit 8051 Protocol Board RS 232 Data Board To be deleted later! Packet, ack, and retransmit Sends byte

5 Protocol Board requires: Protocol Board requires:
RF Message Formats Request DoorModule Badge Response + BadgeID Protocol Board requires: TO/FROM Packet # Packet Size Data Bytes OutBuffer: Request DoorModule InBuffer: RESPONSE BadgeID Protocol Board requires: TO/FROM Packet # Packet Size Data Bytes Request InBuffer: Badge OutBuffer: RESPONSE BadgeID

6 Time Line 8051 (DoorModule) Sonar (DoorModule) Badge FPGA (DoorModule)
INIT ECHO Badge Request Time Response + BadgeID FPGA (DoorModule) Request + BadgeID Check BadgeID

7 Verifing User Reset 8 !Request WAIT_ID ROM (LUT) BadgeID Control BUSY
AUTH = 0 ROM (LUT) BadgeID Control BUSY Request Request seconds == 4 Reset !DB AUTH CHECK_ID BUSY = 1 AUTH = 0 AUTHORIZE BUSY = 1 AUTH = 1 Counter DB

8 Timing Diagram CLK BadgeID REQUEST BUSY AUTH

9 Current Status Done: In progress:
Detect a user within 6 inches to 3 feet. Detect a user within 0.5 second. RF messaging protocol. Built the badge. In progress: Debugging the badge. Implementation and debugging of FPGA.

10 Summary Hand-free and preserve security checking.
Final technical design of the DoorModule and the Badge. Sonar detects user intention. RF exchanges user information. FPGA does the checking. Analysis/data/results show our design will meet the requirement. Current schedule Coming soon…… Product demo. Hope you enjoy the presentation as much as we do. And, I am going to hand it off to our reviewer, group C. Thank you.


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