1. Miss Rate versus Block Size

2. Review

3. CS501 Advanced Computer Architecture
Lecture 39
Dr.Noor Muhammad Sheikh

4. Performance versus Year
µProc
60%/yr.
1000
CPU
“Moore’s Law”
100
Processor-Memory
Performance Gap: (grows 50% / year)
Performance 10
DRAM
7%/yr.
DRAM 1
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
Year

5. Block Diagram of Cache Cache Fast Memory Control Logic Determine and
comparison
unit
Tag
RAM

6. Int ALFA [100], SUM; SUM = 0; For ( i=1; i<=100; i++ ) { SUM = SUM + ALFA[i]; }

7. Associative Cache fig. 7.31(jordan)l i d C a c h e M a i n m e m o r y b i t s m e m o r y m e m o r y 4 2 1 1 C a c h e b l o c k M M b l o c k ? 1 ? M M b l o c k 1 1 1 9 1 2 C a c h e b l o c k 2 M M b l o c k 2 2 1 2 5 5 C a c h e b l o c k 2 5 5 M M b l o c k 1 1 9 T a g O n e c a c h e l i n e , f i e l d , 8 b y t e s M M b l o c k 4 2 1 1 3 b i t s V a l i d , 1 b i t M M b l o c k 8 1 9 1 M a i n m e m o r y a d d r e s s : 1 3 3 O n e c a c h e l i n e , T a g B y t e 8 b y t e s

8. Main memory address references have two fields:
3-bit word field
13-bit tag field

9. 3-bit word field becomes a “cache address”.
Cache address specify where to find the word in the cache.
The 13-bit field must be compared against every 13-bit tag in the tag memory.

10. Associative Cache Mechanism fig. 7.32 (Jordan)b i V l d 6 4 3 8 T o C P U A r g u m e n s v y 1 S B k ? 2 5 O ,

11. Direct-mapped cache
The main memory address is partitioned into three fields:
Word field
Group field
Tag field

12. Direct-mapped cache Cache address is composed of two fields:
Group field
Word field

13. Figure: 7.34
(jordan)

14. Continued
The data cache RAM is a block of fast memory, usually a static RAM and it stores copies of data or instructions frequently requested by the CPU
The Tag RAM contains part of the memory address, called into the data cache RAM.

15. Continued
Associative memories are considerably more expensive in terms of gates than ordinary access-by-address memories
Each bit comparison is made with an XOR gate, whose output will be 0 if there is a match between the two bits.
1 output from the NOR gate indicates a word match.

16. Continued
Valid bit specifies that the information in the selected block is valid

17. Figure:7.33 (jordan)

18. Direct mapped cache fig. 7.33 (Jordan)y M i n b l k u s G p # : V d t 1 2 5 3 9 8 T g f , B O 6 7 4

19. Direct map cache
Imposes a considerable amount of rigidity on cache organization.
Relies on principle of locality.

20. Direct mapped cache Advantage: simplicity Disadvantage:
only a single block from a given group is present in cache at any time.

21. 2-Way Set-Associative Cache fig. 7.35(Jordan)m e m o r y m e m o r y M a i n m e m o r y b l o c k n u m b e r s G r o u p # : 2 3 5 1 2 7 6 8 2 5 6 5 1 2 7 6 8 7 9 3 6 2 9 1 5 1 3 2 3 4 1 2 5 7 5 1 3 2 3 4 7 6 8 1 7 9 3 7 1 1 2 2 5 8 2 2 5 8 5 1 4 7 6 8 2 7 9 3 8 2 1 2 5 5 2 5 5 5 1 1 2 5 5 5 1 1 7 6 7 8 1 9 1 2 5 5 T a g # : 1 2 9 3 3 1 T a g O n e f i e l d , c a c h e 5 b i t s l i n e , O n e c a c h e l i n e , 8 b y t e s 8 b y t e s C a c h e g r o u p a d d r e s s : 8 3 M a i n m e m o r y a d d r e s s : 5 8 3 T a g S e t B y t e

22. Continued
The cache hardware is a combination of direct and associative mapping.

23. Block Replacement

24. 2-Way Set-Associative Cache
Similar to direct mapped cache
Twice as many blocks in the cache so that a set of any two blocks from each main memory can be stored in the cache.

25. 2-Way-Set-Associative Cache
The main memory is address is divided into two fields:
8-bit set field
5-bit tag field

26. Continued The group field is called the set field.
Set field is decoded and direct the search to the correct group.
After that the tags in the selected groups are searched.

27. Continued
Multiple copies of the same data can exist in memory hierarchy simultaneously.
Cache needs updating mechanism to prevent old data values from being used. This is the problem of cache coherence.
Write policy is the method used by the cache to deal with and keep the main memory updated.

28. 2-Way-Set-Associative Cache
Two possible places in which a block can resides.
Both places must be searched associatively.
Cache group address is the same as that of the direct-mapped cache.

29. Continued
Dirty bit is a status bit which indicates whether the block in the cache is dirty.
If the block is clean, it is not written on a miss, since lower level contains the same information as the cache
Writing the cache is not as easy as reading from it, e.g. modifying a block cannot begin unit the tag has been checked to see if the address is a hit

30. Continued
In the case of write through, also called store through, the information is written to both the blocks in the cache as well as in the next lower level memory which is the main memory.
Read misses never results in the write to the lower level
In the next lower level the most current copy of the information is present at all times

31. Continued Write stall:
For write to complete in write through, the CPU has to wait. This wait state is called write stall.
Write buffer:
Write Buffer reduces the write stall by permitting the processor to continue as soon as the data has been written into the buffer, thus allowing overlapping of the instruction execution with the memory update.

32. Continued
Write Back:
The information is written only in lower block from the cache when modified.
The modified block is written to the lower level when it is replaced with the cache.
Write occurs at the speed of the cache memory.
Multiple writes within a block require memory.
It uses less memory bandwidth.

33. Continued Write Allocate:
The block is loaded followed by the write. This action is similar to the road miss. It is used in write back caches, since subsequent writes to that particular block will be captured by the cache.
No write Allocates:
The block is modified in the lower level and not loaded into the cache. This method is generally used in write through caches as subsequent writs to that block still have to go to the lower level