1. Copyright IMEC
Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs)
Submission Title: [A/D Converters for 60 GHz Radio]
Date Submitted: [14 January, 2007]
Source: [André Bourdoux, Geert Van der Plas, IMEC]
Address [Kapeldreef 75, 3001 Leuven, Belgium]
Voice:[ ], FAX: [ ],
Re: []
Abstract: []
Purpose: [Information on Analog-toDigital converter technology]
Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual(s) or organization(s). The material in this document is subject to change in form and content after further study. The contributor(s) reserve(s) the right to add, amend or withdraw material contained herein.
Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P
André Bourdoux

2. A/D converters for 60GHz radio
André Bourdoux
Geert Van der Plas
André Bourdoux

3. A/D research: innovative A/D solution for 60GHz radios
Copyright IMEC
A/D research: innovative A/D solution for 60GHz radios
Radio Receiver
ADC
Analog FE
Digital FE
Energy-efficient, reconfigurable analog-to-digital converters in deep sub-micron CMOS technologies for 60GHz wireless systems
ADC is converting analog continuous time to discrete time discrete amplitude, between analog FE and digital baseband
The mission is: 60 GHz
in the next few slides I will specify what the highlighted words mean in more detail
André Bourdoux

4. Copyright IMEC
The ADC FoM, the energy per conversion step EQ, is the energy efficiency measure
P is the power consumption
empirically EQ has been found to be almost constant for a given technology independent of fsample or effective number of bits (ENOB), hence a FoM.
A value of 1 pJ/step is/was considered good
current best public known value is 0.16pJ/step
This FoM is also our measure for reconfigurable A/D: halving speed should halve power, removing one bit also
what is energy efficieny for an ADC.
Explain Eq in two steps
say it is an empirical measure which is found to be almost constant independent of fsample and enob, for a given tech
1pJ/step, best value ever will be presented by Jan at ISSCC feb next year and is 65 fJ/step
This defines our targets for the AD
André Bourdoux

5. Deep sub-micron CMOS enables better energy efficiency
Copyright IMEC
Deep sub-micron CMOS enables better energy efficiency
FoM is dependent on technology
example: CMOS scaling has enabled reduction from 8.2 pJ/step (0.25u) to 0.16 pJ/step (90nm) for GS/s 4-6b flash converters
Target technology is 65/45nm
invent new or modify existing architectures to exploit the potential energy efficiency enabled by scaling
You might have noticed that I said the energy per conv step is constant for a given technology !
André Bourdoux

6. 60 GHz radios require 4-6 bit, GS/s A/D: Energy Efficiency is at best 0.16 pJ/step
Design
Power [mW]
Resolution
[bit] (ENOB) fs
[GS/s]
ERBW
[MHz]
Proc.
[μm]
FoM (EQ)
[pJ]
Jiang (ISSCC03)
310
6 (4.7) 2
750
0.18
3.5
Scholt. (JSSC02)
340
6 (5.7)
1.6
550 4
Varzagh. (VLSI04) 70
5 (4)
0.6
N/A
7.3
Park (ISSCC 06)
89(+dig)
4 (3.84)
2000
1.55
IMEC (DAC 06)
10.4
4 (3.7) 1
5800
0.8
Chen (VLSI 06)
105
6 (5.0)
400
Okada (ESSC03)
182
4 (N/A)
0.13
2.8
Sandner (JSSC05)
160
6 (5.5)
1.2
700
2.2
Schvan (ISSCC 06)
3000
5 (4.4) 22 14
Chen (ISSCC 06)
5.3
6 (N/A)
4000
0.22
Draxel. (ISSCC04) 10
6 (4.9)
300
0.09
0.54
Figuerei. (ISSCC 06) 55
6 (5.3)
500
1.4
IMEC (ISSCC 06)
2.5
1.25
3300
0.16
Park (CICC 06)
227
5 (3.6)
<1000 18
Ginsburg (VLSI 06) 6
0.5
250
0.065
0.77
André Bourdoux

7. SNDR versus fin, fs=1.25 GS/s
nyquist = 3.7
ERBW = 3.3 GHz
SNDR [dB]
André Bourdoux

8. Spectrum @ nyquist, fs=1.25 GS/s
SFDR = 36 dB
2500pts
André Bourdoux

9. Zoom-in on waveform @ 3.6 GHz, fs=1.25 GS/s
André Bourdoux

10. In 65/45 nm CMOS, A/D consume ~10 mW if we can maintain energy efficiency @ 0.1pJ
Assume a 0.1 pJ/step energy efficiency
a 4b, 4GS/s A/D  ~6.4 mW
a 5b, 2GS/s A/D  ~6.4 mW
a 6b, 2GS/s A/D  ~12.8 mW
etc.
1 mW
10 mW
100 mW
André Bourdoux

11. A/D technology can reach the 0.1pJ target in 65nm
two power supplies buffer & core (both 1.8V for 0.18u)
single-ended time multiplexed outputs (2)
serial input data & clock
Chip: 4b 1GS/s 0.8pJ in 0.18u, 4b 1.25GS/s 0.16pJ in 90nm
single-ended clock input
differential input
André Bourdoux

12. Designs in the pipeline
two 90nm designs are planned for early next year (tape out Q1 2007)
5b ~2GS/s target power 10mW (0.15 pJ/step)
6b ~1GS/s target power 10mW (0.15 pJ/step)
65nm designs (tape out Q3 2007)
increase sampling speed and improve energy efficiency (0.1pJ/step)
André Bourdoux

13. References
Van der Plas, G.; Decoutere, S.; Donnay, S., “A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process”, ISSCC 2006
André Bourdoux