1. Chapter 2 Instructions: Language of the Computer part 2
박능수

2. Conditional Operations
The University of Adelaide, School of Computer Science
10 January 2019
Conditional Operations
Branch to a labeled instruction if a condition is true
Otherwise, continue sequentially
beq rs, rt, L1
if (rs == rt) branch to instruction labeled L1;
bne rs, rt, L1
if (rs != rt) branch to instruction labeled L1;
j L1
unconditional jump to instruction labeled L1
Chapter 2 — Instructions: Language of the Computer

3. Compiling If Statements
The University of Adelaide, School of Computer Science
10 January 2019
Compiling If Statements
C code:
if (i==j) f = g+h; else f = g-h;
f, g, … in $s0, $s1, …
Compiled MIPS code:
bne $s3, $s4, Else add $s0, $s1, $s j Exit Else: sub $s0, $s1, $s2 Exit: …
Assembler calculates addresses
Chapter 2 — Instructions: Language of the Computer

4. Compiling Loop Statements
The University of Adelaide, School of Computer Science
10 January 2019
Compiling Loop Statements
C code:
while (save[i] == k) i += 1;
i in $s3, k in $s5, address of save in $s6
Compiled MIPS code:
Loop: sll $t1, $s3, add $t1, $t1, $s lw $t0, 0($t1) bne $t0, $s5, Exit addi $s3, $s3, j Loop Exit: …
Chapter 2 — Instructions: Language of the Computer

5. Basic Blocks A basic block is a sequence of instructions with
No embedded branches (except at end)
No branch targets (except at beginning)
A compiler identifies basic blocks for optimization
An advanced processor can accelerate execution of basic blocks

6. MIPS Control Flow Instructions
MIPS conditional branch instructions:
bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1
Ex: if (i==j) h = i + j;
bne $s0, $s1, Lbl1 add $s3, $s0, $s1 Lbl1: ...
Instruction Format (I format):
How is the branch destination address specified?
0x bit offset

7. Specifying Branch Destinations
Use a register (like in lw and sw) added to the 16-bit offset
which register? Instruction Address Register (the PC)
its use is automatically implied by instruction
PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction
limits the branch distance to -215 to (word) instructions from the (instruction after the) branch instruction, but most branches are local anyway PC
Add 32
offset 16 00
sign-extend
from the low order 16 bits of the branch instruction
branch dst
address ? 4

8. In Support of Branch Instructions
We have beq, bne, but what about other kinds of branches (e.g., branch-if-less-than)? For this, we need yet another instruction, slt
Set on less than instruction:
slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1 else # $t0 = 0
Instruction format (R format):
Alternate versions of slt
slti $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...
sltu $t0, $s0, $s1 # if $s0 < $s1 then $t0=1 ...
sltiu $t0, $s0, 25 # if $s0 < 25 then $t0=1 ...
x24 2

9. Aside: More Branch Instructions
Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions
less than blt $s1, $s2, Label
less than or equal to ble $s1, $s2, Label
greater than bgt $s1, $s2, Label
great than or equal to bge $s1, $s2, Label
Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler
Its why the assembler needs a reserved register ($at)
slt $at, $s1, $s2 #$at set to 1 if
bne $at, $zero, Label #$s1 < $s2

10. Bounds Check Shortcut
Treating signed numbers as if they were unsigned gives a low cost way of checking if 0 ≤ x < y (index out of bounds for arrays)
sltu $t0, $s1, $t2 # $t0 = 0 if $s1 > $t2 (max) # or $s1 < 0 (min) beq $t0, $zero, IOOB # go to IOOB if # $t0 = 0
The key is that negative integers in two’s complement look like large numbers in unsigned notation. Thus, an unsigned comparison of x < y also checks if x is negative as well as if x is less than y.

11. Other Control Flow Instructions
MIPS also has an unconditional branch instruction or jump instruction:
j label #go to label
Instruction Format (J Format):
0x bit address PC 4 32 26 00
from the low order 26 bits of the jump instruction

12. Aside: Branching Far Away
What if the branch destination is further away than can be captured in 16 bits?
The assembler comes to the rescue – it inserts an unconditional jump to the branch target and inverts the condition
beq $s0, $s1, L1
becomes
bne $s0, $s1, L2
j L1
L2:

13. Instructions for Accessing Procedures
MIPS procedure call instruction: jal ProcedureAddress #jump and link
Saves (PC+4) in register $ra to have a link to the next instruction for the procedure return
Jump to target address
Machine format (J format):
Then can do procedure return with a
jr $ra #return
Copies $ra to program counter
Can also be used for computed jumps
e.g., for case/switch statements
Instruction format (R format):
0x bit address
x08

14. Six Steps in Execution of a Procedure
Main routine (caller) places parameters in a place where the procedure (callee) can access them
$a0 - $a3: four argument registers
Caller transfers control to the callee
Callee acquires the storage resources needed
Callee performs the desired task
Callee places the result value in a place where the caller can access it
$v0 - $v1: two value registers for result values
Callee returns control to the caller
$ra: one return address register to return to the point of origin

15. Leaf Procedure Example
The University of Adelaide, School of Computer Science
10 January 2019
Leaf Procedure Example
C code:
int leaf_example (int g, h, i, j) { int f; f = (g + h) - (i + j); return f; }
Arguments g, …, j in $a0, …, $a3
f in $s0 (hence, need to save $s0 on stack)
Result in $v0
Chapter 2 — Instructions: Language of the Computer

16. Leaf Procedure Example
The University of Adelaide, School of Computer Science
10 January 2019
Leaf Procedure Example
MIPS code:
leaf_example: addi $sp, $sp, sw $t1, 8($sp) sw $t0, 4($sp) sw $s0, 0($sp) add $t0, $a0, $a1 add $t1, $a2, $a3 sub $s0, $t0, $t1 add $v0, $s0, $zero lw $s0, 0($sp) lw $t0, 4($sp) lw $t1, 8($sp) addi $sp, $sp, 12 jr $ra
Save $t1 on stack
Save $t0 on stack
Save $s0 on stack
Procedure body
Result
Restore $s0
Restore $t0
Restore $t1
Return
Chapter 2 — Instructions: Language of the Computer

17. The University of Adelaide, School of Computer Science
10 January 2019
Non-Leaf Procedures
Procedures that call other procedures
For nested call, caller needs to save on the stack:
Its return address
Any arguments and temporaries needed after the call
Restore from the stack after the call
Chapter 2 — Instructions: Language of the Computer

18. Non-Leaf Procedure Example
The University of Adelaide, School of Computer Science
10 January 2019
Non-Leaf Procedure Example
C code:
int fact (int n) { if (n < 1) return f; else return n * fact(n - 1); }
Argument n in $a0
Result in $v0
Chapter 2 — Instructions: Language of the Computer

19. Non-Leaf Procedure Example
The University of Adelaide, School of Computer Science
10 January 2019
Non-Leaf Procedure Example
MIPS code:
fact: addi $sp, $sp, # adjust stack for 2 items sw $ra, 4($sp) # save return address sw $a0, 0($sp) # save argument slti $t0, $a0, # test for n < beq $t0, $zero, L1 addi $v0, $zero, 1 # if so, result is addi $sp, $sp, # pop 2 items from stack jr $ra # and return L1: addi $a0, $a0, # else decrement n jal fact # recursive call lw $a0, 0($sp) # restore original n lw $ra, 4($sp) # and return address addi $sp, $sp, # pop 2 items from stack mul $v0, $a0, $v0 # multiply to get result jr $ra # and return
Chapter 2 — Instructions: Language of the Computer

20. Aside: Spilling Registers
What if the callee needs to use more registers than allocated to argument and return values?
callee uses a stack – a last-in-first-out queue
high addr
One of the general registers, $sp ($29), is used to address the stack (which “grows” from high address to low address)
add data onto the stack – push
$sp = $sp – data on stack at new $sp
remove data from the stack – pop
data from stack at $sp $sp = $sp + 4
top of stack
$sp
low addr

21. Aside: Allocating Space on the Stack
The segment of the stack containing a procedure’s saved registers and local variables is its procedure frame (aka activation record)
The frame pointer ($fp) points to the first word of the frame of a procedure – providing a stable “base” register for the procedure
$fp is initialized using $sp on a call and $sp is restored using $fp on a return
high addr
$fp
Saved argument regs
(if any)
Saved return addr
Saved local regs
(if any)
Local arrays & structures (if any)
$sp
low addr

22. Aside: Allocating Space on the Heap
Static data segment for constants and other static variables (e.g., arrays)
Dynamic data segment (aka heap) for structures that grow and shrink (e.g., linked lists)
Allocate space on the heap with malloc() and free it with free() in C
Memory
$sp
0x 7f f f f f f c
Stack
Dynamic data
(heap)
$gp 0x
Static data 0x
Text
(Your code) PC 0x
Reserved 0x

23. MIPS Instruction Classes Distribution
Frequency of MIPS instruction classes for SPEC2006
Instruction Class
Frequency
Integer
Ft. Pt.
Arithmetic
16%
48%
Data transfer
35%
36%
Logical
12% 4%
Cond. Branch
34% 8%
Jump 2% 0%

24. Atomic Exchange Support
Need hardware support for synchronization mechanisms to avoid data races where the results of the program can change depending on how events happen to occur
data races : Two memory accesses from different threads to the same location, and at least one is a write
Atomic exchange (atomic swap) – interchanges a value in a register for a value in memory atomically, i.e., as one operation (instruction)
Implementing an atomic exchange would require both a memory read and a memory write in a single, uninterruptable instruction. An alternative is to have a pair of specially configured instructions
ll $t1, 0($s1) #load linked
sc $t0, 0($s1) #store conditional

25. Atomic Exchange with ll and sc
If the contents of the memory location specified by the ll are changed before the sc to the same address occurs, the sc fails (returns a zero)
If the value in memory between the ll and the sc instructions changes, then sc returns a 0 in $t0 causing the code sequence to try again.
try: add $t0, $zero, $s4 #$t0=$s4 (exchange value)
ll $t1, 0($s1) #load memory value to $t1
sc $t0, 0($s1) #try to store exchange #value to memory, if fail #$t0 will be 0
beq $t0, $zero, try #try again on failure
add $s4, $zero, $t1 #load value in $s4

26. Translation and Startup
The University of Adelaide, School of Computer Science
10 January 2019
Translation and Startup
Many compilers produce object modules directly
Static linking
machine code
Chapter 2 — Instructions: Language of the Computer

27. Compiler Benefits Comparing performance for bubble (exchange) sort
To sort 100,000 words with the array initialized to random values on a Pentium 4 with a 3.06 clock rate, a 533 MHz system bus, with 2 GB of DDR SDRAM, using Linux version
The unoptimized code has the best CPI, the O1 version has the lowest instruction count, but the O3 version is the fastest.
gcc opt
Relative
Performance
Clock
cycles (M)
Instr count (M)
CPI
None
1.00
158,615
114,938
1.38
O1 (medium)
2.37
66,990
37,470
1.79
O2 (full)
2.38
66,521
39,993
1.66
O3 (proc integ)
2.41
65,747
44,993
1.46

28. Addressing Mode Summary
The University of Adelaide, School of Computer Science
10 January 2019
Addressing Mode Summary
Chapter 2 — Instructions: Language of the Computer

29. MIPS Organization So Far
Processor
Memory
Register File
1…1100
src1 addr
src1
data 5 32
src2 addr 32
registers
($zero - $ra) 5
dst addr
read/write
addr 5
src2
data
write data 32
230
words 32 32
32 bits
branch offset
read data 32
Add PC 32 32 32 32
Add 32 4
write data
0…1100
Fetch
PC = PC+4
Decode
Exec 32
0…1000 32 4 5 6 7
0…0100 32
ALU 1 2 3
0…0000 32
word address
(binary)
32 bits 32
byte address
(big Endian)