1. Hot Carrier Effects in Small Channel MOSFETs
As MOS is scaled, the E-field between the pinch-off region and the drain becomes very large. Carriers traveling in this region will then gain large amounts of energy and become “hot”, i.e. highly energetic.

2. Two “potential” events:
Hot carriers may eventually be scattered, and be deflected toward the gate. If these carriers have enough energy, they will surmount the SiO2 interface and be injected into SiO2.
Þ (a) gate currents
(b) interface-state formation
(c) oxide-trapped charge

3. Some of the carriers will eventually get enough energy to cause impact ionization:
(a) extra electron will give rise to a small increase in ID
(b) holes Þ substrate currents

4. In the extreme case, it can also cause source-drain breakdown.
If the source-to-substrate forward bias, VBE, in the figure above reaches ≈ volts, we will have bipolar action (i.e. source → emitter, substrate → base, drain → collector). Breakdown will occur when anpn M = 1, where anpn is the common-base current gain ≈ 1-L2/(2Leff) ≈ 1, and M is the multiplication factor due to impact-ionization.

5. Modeling of the substrate currents and gate currents
The key problems of the hot carriers are the degradations of the gate oxide and oxide/silicon interface. Gate oxide wear-out is due to the “gate currents” which are generated by the hot carriers near the drain. Since hot carriers also create the substrate currents, we expect that gate currents and substrate currents are correlated. Since IG is usually small and hard to measure, we typically measure Isub and use it as a monitor for hot carrier effects. To model these hot carriers, we start with the “lucky electrons (carriers) models”.
The basic idea, called the “lucky electron model”, is from Shockley: if an electron can survive a large distance in a high field region without scattering, it will become very hot. Shockley’s equation of the probability of an electron without being scattered in a distance (d) is:

6. In the above equation, le is called the lucky electron mean-free path
In the above equation, le is called the lucky electron mean-free path. In an equivalent form, i.e., changing it into the energy (hot carrier) probability, we have:

7. Thus, we see that
Change the integral into energy form:
where

8. For gate currents, there are three possible mechanisms:
Channel Hot Carriers (CHE)
Drain Avalanche Hot Carriers (DAHC)
Secondarily Generated Hot Carriers (SGHC)
Channel hot carriers’ origin is similar to that of substrate currents. Namely, lucky electrons near the drain junction suffered an elastic scattering. They travel towards the SiO2/Si interface. When energy is high enough, the electrons are injected into the oxide and resulted in gate currents. Note that CHE is less likely for VG £ VD, since the gate-to-drain electric field will repulse the electrons.

9. To model CHE, the procedure is similar to that of substrate currents, except that we need an additional integral to account for the probability of surmounting the Si/SiO2 interface:
where
Hence, we have

10. The correlation is correct for VGS > VDS -0
The correlation is correct for VGS > VDS -0.5V, because as VDS increases, the oxide field Eox near the drain changes sign, and the above equation for Igate is no longer valid. In reality, Igate due to CHE is negligible for VGS £ VDS -0.5V, and under such condition, DAHC dominates.

11. Under DAHC, significantly more hot carriers (both electrons and holes) are generated by impact ionization and these carriers are injected towards the Si/SiO2 interface. In this regime, the “source” of the gate currents is the substrate currents (rather than IS) and the gate currents are given by:
where x(Ex,Ey) is the intrinsic injection ratio. xe(Ex,Ey) (and similarly for xh(Ex,Ey) can be expressed as
P is the injection probability that an carrier striking the Si/SiO2 interface to have energy EB greater than qFB (qFB is the Si-SiO2 energy barrier: 3.2 eV for electrons and 3.7 eV for holes), and S is the scattering factor: the probability that these carriers striking the Si-SiO2 interface will move into the oxide, avoiding the refection.

12. The injection ratio, gA, has been determined experimentally and has a simple dependence on VG. The carrier temperatures can be estimated by:
where
lr is the mean free path (~6nm) , Er is the Raman optical phonon energy (~0.063eV), and r is the ratio of lr to the impact-ionization mean free path (~3.2)

13. P is found experimentally to be
with A=1.874 and B=0.926
The scattering factor S is given by
where q is the angle between the electric field and the normal to the Si/SiO2 interface. f0 and f1 are the zero and first-order harmonics of the distribution function in momentum space. As mentioned above, gA is an exponential function of VG and exhibits different behaviors for electrons and holes. With these equations, we can simulate the gate currents under the DAHC regime. Agreement between measured gate currents and simulation is remarkable in spite of the large number of variables involved in this injection process.

15. For small VD and with VG > VD , we have SGHC
For small VD and with VG > VD , we have SGHC. The origin of SGHC is also impact ionization. During impact ionization, photons are generated, most likely through the bremsstrahlung radiation. These photons can generate electron-hole pairs near the depletion edge on the drain-side. As the electrons travel across the depletion region with high electric fields, they become hot carriers. However, the gate current is small.

16. The consequence of the correlation between the gate and the substrate currents is that by measuring the substrate current, the size of the gate current can be inferred. That is, Isub is a “good” monitor for the hot carrier effects on the degradation of the devices (e.g. interface states generation and oxide fixed charges)! Note that the correlation is not perfect (especially for PMOS devices).

17. The current understanding of the Hot-carrier induced degradation is:
Hot holes injecting towards the SiSiO2 interface, creating a trapped hole.
Hot electrons annihilate the trapped hole, creating a neutral interface trapped
Electrons trapped by the Interface trap, it becomes a scattering center (lowering the gm) and also shifts the Vth.
In all cases, it was found that the degradation rate under DC bias follows:

18. n ≈ 0.5 for nMOSFET under the maximum degradation conditions for fixed VD : (VG ≈ VD/2, i.e. DAHC) and A is correlated to Isub and therefore is a strong function of VD given by

19. the most important parameter to determine IG/sub/IS is Emax, the maximum electrical field. To obtain Em, one needs to solve the 2-D Poisson’s equation near the drain:

20. This can be solved using 2-D simulation, such as PISCES or MINIMOS
This can be solved using 2-D simulation, such as PISCES or MINIMOS. However, it is important to have an analytic expression for physical insights.
One way to get the information is to assume that near the drain:
We then obtain
with E = 0 at y = L - DL and

21. If we ignore n, we get the Sah/Pao channel length modulation formalism – which is incorrect! One of the difficulties that can easily be seen is that, in the channel and up to “pinch-off”, E goes to ¥, and at the pinch-off point E is zero by the B.C.

22. A small correction is to include n by setting
where a is a fitting parameter. However, with this modification, E(y) is still a linear function of y, which does not correctly describe the exponential behavior of Ey near the drain.
What needs to be done is to use a pseudo-two dimensional model proposed by Elmansy, and later by Ko (see, for example, IEEE TED ED-34, p. 1509, 1987). This has the effect of including the variation in the oxide fields.

23. Applying the Gauss law to the rectangle ABCD:
Differentiating both sides

24. We also have (gradual channel approximation):
Put this into the differential equation, we get:

25. But
where
Similarly

26. At the drain end, Ey is maximum and therefore Em is given by:
From the equation for V(y’), we have: If

27. Therefore, to minimize hot carrier effects, we need to minimize 1/l or to maximize tox1/2xj1/2 (2-D simulation gives tox1/2xj1/3).
But this is contrary to the requirements for good device performance and small DIBL Þ must look for alternative way to solve the hot carrier effects!
Note also that, since the ionization coefficient for holes is less than the ionization coefficient for electrons, the measured Isub is ≈103 times less in PMOS. This is also due in part to the smaller m of the hole. Also, if hot carriers are generated, there is a larger barrier for holes → SiO2 than for electrons ( 3.6 eV vs. 3.2 eV). Thus, PMOS is likely to be more reliable.

28. To alleviate the problem of hot carrier effects, various schemes were proposed:
Drain engineering (e.g. LDD structure): From pn junctions, we notice that the E µ doping. Hence, to reduce the Emax in the drain region, we have an (ND)- region, so that the drain junction looks like:
Several ways were used to achieved these drain structures. The common method used to achieve drain engineering is to use a side-wall spacer (older techniques include double-diffused drain):

29. Note that the maximum E-filed is reduced: Since Em is reduced, we expect the hot electron density ¯ Þ less hot carrier- induced problem. Also, Isub ¯ since there is less impact ionization

30. Problems with this approach are:
is smaller due to series resistance in the n- region. This can be very important, especially for small MOS devices.
If an oxide-trapped charge is in the side-wall region, then VTH is modified a great deal, since the gate is the only marginal control over that portion of the interface underneath the side-wall spacer.
The second approach is to make the gate insulator more “hard” against hot carrier-induced defects, including using nitridation and fluoridation. The idea is to improve the “strength” of the oxide.