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Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012

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1 Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012
An Ultra-Low-Voltage CMOS Mixer Using Switched-Transconductance Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting Techniques Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012

2 Above Picture : Smart Stents, SoC and MEMS lab, UBC
Big Picture Designing Building Blocks for Ultra-Low–Voltage/Power CMOS RF Front-End for applications such as: Biomedical Application Above Picture : Smart Stents, SoC and MEMS lab, UBC Low Power Wireless Communication

3 Outline Overview of Conventional Active Mixers Overview of techniques
Stack Reduction, LO-Gm Separation Current-Reuse Dynamic Threshold Mixer Design Gm-Stage - Double Balanced Current Reuse Gilbert Structure LO -Stage - Switched Supply Voltage Post-Layout Simulation Results and Comparison Concluding remarks

4 Conventional Active Mixers
Gilbert-Type Mixer (Current commutating) 3 stacked transistors  each transistor VDS is around VDD/3 Considering Vth is around 0.4 V, minimum supply voltage is around 1.2 V To increase conversion gain (CG) one can increase load (CGαRL×) Penalty: more voltage drop across load  trade-off between VDD and CG Mixer core is always ON (For Biasing the transistors) Reduce the voltage drop across the Load Resistor to increase M1 drain Voltage Even more challenging if IIP3 has to be improved Challenge of biasing current source in saturation for low supply voltage (e.g. VDD < 1.5) Limitations for Supply-Voltage: Power Consumption issue:

5 Supply Voltage (V) – Year (1997-2012)
Bulk_Driven and Folded Methods Very Low CG (1<CG<9) Roughly Reduction of V/Year y = x Range of Threshold Voltage

6 Mixer Power (mW)– Year (1997-2012)
y = x Roughly a reduction of 0.88 mW/Year (it is leveling off)

7 Design Bottlenecks Stacked Architectures : For decreasing Supply Voltage we should reduce Number of transistor Stacked stages , we have different methods , below we bring ONLY two of them : Bulk-Driven Method Low Conversion Gain (Mostly below 10) Constant Biasing Current Folded Gilbert Architecture Moderate Conversion Gain – Wide Band Bulky Inductors Threshold Voltage : If decreases the headroom will increases, so it would be nice if we have lower threshold Voltage We can't find any significant publication for reducing threshold voltage in Mixers

8 Proposed Techniques for Ultra Low Voltage Mixer
Reducing Stacked Transistors by Switched Transconductance: LO-Stage and Gm-Stage can be separated by switching supply voltage of Gm-Stage Turn ON & Off Gm-Stage with LO  Save Power Gm ON/OFF Approach Current Commutating Approach


10 Proposed Techniques for Ultra-Low-Voltage Mixer
Choosing Gm-Stage, Maximizing Conversion Gain and Linearity: Pick a proper Gm-Stage for High Conversion Gain (High output Gm) and High Linearity  Current-Reuse technique Overal Gm = gmn+gmp Linearity will be improved Total Gm=gmn Total Gm=gmn+gmp Current-Reuse is similar to Push-Pull Buffer

11 Switching Stage Inverter with Dynamic Threshold-Voltage:
We should implement a switch between VDD and GND Different Options : Simple Digital Inverter High-speed comparator (compare LO with GND, requires low LO power) Inverter with Dynamic Threshold-Voltage: Reduce VTH of NMOS transistors by connecting inverter output to body of NMOS (DTMOS) Output voltage of the inverter with CL=1pF, PLO= −8 dBm, 2.45 GHz LO signal and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b) without DTMOS. .

12 Proposed Building Block For ULV Mixer

13 Proposed Double-Balanced Design

14 Post-Layout Simulation Results
Case 1 : Sub Threshold Case 2 : Case 3 : Super Case 4 : Case 5 : VDD (V) 0.35 0.4 0.5 0.8 1.2 VBN (V) 0.40 0.47 0.75 VBP (V) 0.00 0.6 PLO (dBm) -3.75 -4.00 - 4.1 -6.6 -7.5 NF (dB) 12.7 11.2 10.56 12 11.1 CG (dB) 13 14.7 15.8 15.2 17.3 IIP3 (dBm) -3.08 -5.54 -8.6 -7.04 -8.1 PDC (mW) 0.48 1.6 3.4 IBM0.13-µm CMOS VTH≈ 0.42 V

15 Effect of Dynamic Threshold Technique

16 Conversion Gain at Different Supply Voltages

17 LO-Gm Separation Method Conventional Inverter
Parameters This Work* JSSC RFIC MTT LO-Gm Architecture Separated Stacked Folded LO-Gm Separation Method DTMOS Inverter Conventional Inverter N/A Gm-Stage Current Reuse NMOS RF (GHz) 2.5 2.01 2.4 5.3 8.6 IF (MHz) 50 10 60 1 4350 PLO(dBm) −3.75 −4.1 −4 −9 −2.0 −3.6 −3.3 VDD(V) 0.35 Subthreshold 0.5 1 Subthreshold 1.8 0.9 0.6 PDC(mW) 0.48 1.6 8.1 6.6 NF (dB) 12.7 10.56 23.7 18.3 12.9 24 15.9 IIP3(dBm) −3.08 −8.6 7 −11.6 −8 Conversion Gain (dB) 13 15.8 9.8 15.7 8.9 6 CMOS Technology (µm) 0.13 0.18 FOM1 / FOM2 31.65 / 26.3 25.78 / 22 18.62 / 17.83 22.15/ 21.36 14.41 / 16.17 1.75 / 0.50 24.32 /21.31

18 Techniques to improve mixer performance:
Concluding Remarks Techniques to improve mixer performance: Reduce stacked levels For Gm-Stage , try to choose blocks with higher output Gm and Linearity Reduce VTH by body effect (Dynamic Threshold Technique), Both for Gm-Stage and LO-Stage, so we can use it for increasing headroom an Turn-off circuit when you don’t want to use it to save power TSMC 90nm Process RF LO VDD (V) 0.3 PLO (dBm) -8.4 CG (dB) 27-15 Frequency DC-12GHz PDC (mW) 0.09 mWatt IF+ Active Balun IF- Resonator Buffer Mixer Core Resonator

19 And thank you for listening!
Acknowledgments NSERC CMC Microsystems IBM TSMC And thank you for listening!

20 References E.A.M. Klumperink, S.M. Louwsma, G.J.M. Wienk, and B. Nauta, “A CMOS switched transconductor mixer,“ IEEE Journal of Solid-State Circuits, ­­­vol.39, no.8, pp , Aug Hanil Lee; Mohammadi, S., “A 500μW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp , 3-5 June 2007. Kihwa Choi; Dong Hun Shin; Yue, C.P., “A 1.2-V, 5.8-mW, Ultra-Wideband Folded Mixer in 0.13-μm CMOS,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp , 3-5 June 2007. Assaderaghi, F.; Sinitsky, D.; Parke, S.A.; Bokor, J.; Ko, P.K.; Chenming Hu; "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI ," Electron Devices, IEEE Transactions on , vol.44, no.3, pp , Mar 1997. V. Vidojkovic, et al., “A Low-Voltage Folded-Switching Mixer in 0.18-um CMOS, “ IEEE J. Solid-State Circuits, vol. 40, pp , June 2006.  S. He and C.E. Saavedra, “An Ultra-Low-Voltage and Low-Power  2 Subharmonic Downconverter Mixer,”  IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 2, pp , Feb M. Huang, et al., "A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Applications," IEEE Trans. Microwave Theory Tech., vol. 54, no. 2, pp , Feb  

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