1. Is Co-existence Possible?
David White

2. Virtual Manufacturing Use Model
Calibration Step
Prediction Step
Data from ECD
& CMP Processing Results
ECD/CMP
Virtual Mfg
Process Library
Fabricate
Test Wafer
(ECP/CMP)
Measurement
Data From Test Wafer
Product Design Layout File
Test Wafer
Design Layout File
Predict
New Design
Calibrate
Model
Geometry
Extraction
Geometry
Extraction
The typical customer engagement model is to calibrate the ECD and CMP process flow by processing test wafers and measuring them after each step. The measurements are imported into a calibration tool that generates the VMP library specific to the customers particular process flow.
Full-Chip
Prediction
Semi-Physical Model Tailored to Specific Process
ECD/CMP
Virtual Mfg
Process Library
Tailored to Customer’s Process & Design
Topographical Analysis
December 30, Cadence Confidential: Cadence Internal Use Only

3. What Are Pattern-Process Interactions
Structures with Same Line widths, Same Local Density, and Same Polish Conditions Have Very Different Cu Loss
Memory
Analog
IP Blocks
CPU
Block
Rotated
IP Block
High
If the estimating the variation in thickness was as simple as characterizing the local linewidth and densities, modeling the variation would be straight-forward. However for processes such as CMP, the length scales where the topography and design geometry in one region can impact another can be a millimeter or larger. To illustrate this impact, we worked with one of our customers to create the layout shown here. A prediction of thickness across the chip was generated using models that had been validated in-silicon on this customer’s 90nm products. A CPU block was added in six positions and rotated 90 degrees at two positions. An analog block was repeated along both sides and memory added along the top. Note that the same features within each CPU block can have very different thickness based on its proximity to the dense routing area in the middle or more sparse routed areas along the top and bottom of the CPU positions. Also note that the variation in the analog block changes based on its proximity to the CPU blocks and more dense routed areas.
Thickness
Low
IITC 2005, Nagaraj NS: “Copper and Low k Scaling Challenges: A Design Perspective”
December 30, Cadence Confidential: Cadence Internal Use Only

4. Accounting For Variation in Design Process
Actual Thickness
+20%
Systematic
Thickness
Manufacturing
Variation
Guardband
Systematic &
Random
Thickness
Manufacturing
Variation
Guardband
-20%
Current “2D” Methodology is Conservative Full Chip Guardband
for Both Systematic and Random Thickness Variation (+- 20%)
Random
Thickness
Manufacturing
Variation
Guardband
Our design customers want to know how to account for thickness variation in their designs. In formulating guardbands, measurements are taken to estimate the maximum and minimum within-chip thickness variation. Typically this is done using test chips or test structures and estimates of wafer-level, wafer-to-wafer and random variation are also added into the total thickness guardband. With our solution the systematic within-chip variation is characterized as a function of each feature’s spatial location within the chip and then provided to an RC extraction tool. As shown in the bottom panel, the RC extraction tool adds in the random, uncharacterized, variation guardband to the systematic characterization, thus providing a more accurate characterization and reducing the effective guardband for each respective feature.
+10%
Actual Thickness
-10%
Cadence “3D” Methodology Eliminates Systematic Guardband
Leaving Only a Relatively Small Random Thickness Variation (+- 10%)
December 30, Cadence Confidential: Cadence Internal Use Only

5. Experimental Results: CMP Aware Routing
CMP variation
On average 7.5% reduction
Up to 10.1% reduction
Timing
On average 7% reduction
Up to 10% reduction
[Cho et al, ICCAD’06]
December 30, Cadence Confidential: Cadence Internal Use Only

6. Rules versus Models as Function of Pattern-Process Dependent Interaction
Non-linear, multi-dimensional process or system
MORE
(Volumes)
HIGH
Complexity
Complexity
Value of Models
Value of Rules
LESS
LOW
LOCAL
Process Interaction
GLOBAL
December 30, Cadence Confidential: Cadence Internal Use Only

7. Deficiencies with Pure Rules Based Approach
Little Value Back to Manufacturing
Results in Loss of Accuracy
Characterization of Pattern-Process Behavior
Manufacturing
Customer
Capturing all meaningful interactions into rules
Pattern
Geometries
Design
Rules
Violations & Scoring Metrics
Design
Tools
Local versus global interactions
Design
Customer
December 30, Cadence Confidential: Cadence Internal Use Only

8. Deficiencies with Pure Model Based Approach
Significant Value Back to Manufacturing
Characterization of Pattern-Process Behavior
Manufacturing
Customer
No Filtering of Data
Speed?
Volumes
of Data
(width and thickness dimensions)
Pattern
Geometries
Process
Models
Design
Tools
e.g. 25M thickness
values
What to do with Data? How does it impact my design?
Why does speed have question mark?
To be addressed later
Results in Speed and Data Issues
Design
Customer
December 30, Cadence Confidential: Cadence Internal Use Only

9. Rules and Models Not Mutually Exclusive
Significant Value Back to Manufacturing
Characterization of Pattern-Process Behavior
Manufacturing
Customer
Volumes
of Data
(width and thickness dimensions)
Global Pattern
Geometries
Process
Models
Accuracy
Local Pattern
Geometries
Design
Rules
Violations & Scoring Metrics
Design
Tools
Speed
Design
Customer
December 30, Cadence Confidential: Cadence Internal Use Only

10. 65nm Rule Deck Example
Ran three separate 65nm rule decks on 65nm production design
96% of operation counts are done with 0 halo size
Density rules using 100 micron window size are less than 1% of overall operations but 5% of overall execution time
Halo Size
December 30, Cadence Confidential: Cadence Internal Use Only

11. Backup / Q&A
December 30, Cadence Confidential: Cadence Internal Use Only

12. Models Complement Rules
Design Rules Say OK, Models Say Its Not Acceptable
Metal 4 Copper Density
Metal 4 Copper Loss
0.70  1200A
0.70  2500A
In many cases, design rules which are based on layout geometries such as densities are not sufficient. This slide shows a prediction of metal 4 copper loss using in-silicon validated models and identifies two regions with 70% density that have very different copper loss. It is not uncommon for process effects that are both global and complex to present difficulties for rule-based characterization. Our approach is not to completely replace design rules but to complement them with models.
Both Areas Have 70% Average Density
But Very Different Copper Loss
1200A
2500A
December 30, Cadence Confidential: Cadence Internal Use Only

13. Process for Forming Interconnect (Wires)
Features Defined Through
Lithography and Etch
dielectric
copper
ECD Copper Plating
Step 1: Copper Plating
dielectric
Copper CMP (Bulk)
Step 2: Bulk Polish
Copper CMP (Touchdown)
Step 3: Copper Clear or Touchdown
Copper CMP (Barrier)
Step 4: Barrier Removal
December 30, Cadence Confidential: Cadence Internal Use Only

14. Rules versus Models as Function of Uncertainty in Process Characterization
Non-linear, multi-dimensional process or system
MORE
(Volumes)
HIGH
Value of Models
Value of Rules
LESS
LOW
POORLY
CHARACTERIZED
UNSTABLE PROCESS
Process Maturity
WELL
CHARACTERIZED
STABLE PROCESS
December 30, Cadence Confidential: Cadence Internal Use Only

15. Chemical Mechanical Polishing
Force
Modern polishing heads have separate rings where the force can be radially adjusted
Table with Pad Rotating
Within-Chip Variation: dominated by layout, pad and slurry interaction
Within-Wafer Variation: dominated by pressure zone apportionment in carrier and relative velocities of carrier and table
December 30, Cadence Confidential: Cadence Internal Use Only

16. Interconnect Variation
Wafer Level
Variation
Wafer Surface
Within-Chip Variation is Huge!
Thickness Variation: 10% to 30%
Width Variation: 10% to 30%
Due to Design Impact on Manufacturing
Varying Feature Density
Varying Feature Widths
Variation Leads to Over-Compensation in Design
Timing Failures
Decreased Performance
Increased Power Consumption
Chip Surface
Within-Chip
Variation
Interconnect variation has significant impact on performance and yield. The graphic in the upper right plots topographical variation across a measured wafer. The first effect that may be noticed is the bowl or curve shape of thickness across the wafer. This is wafer-level variation and it results from systematic variation mainly caused by the CMP tool. The second effect that is observed is the larger periodic variation at each die location. In the graphic in the lower right, the within-chip variation is plotted that results from interaction between the design layout patterns and the manufacturing process. Like wafer level variation, within-chip variation is systematic in nature which means it can be characterized and predicted. There are two common characteristics that dictate the within-chip copper and dielectric thickness variation, dishing where copper is selectively removed as an isolated line grows wider and erosion where higher densities promote the removal of both copper and dielectric materials in a local region or array of lines.
Oxide Loss
Dishing
Erosion
Total Copper Loss
Isolated Thin-Lines
Isolated Wide-Lines
Dense Array Thin-Lines
Dense Array Wide-Lines
December 30, Cadence Confidential: Cadence Internal Use Only

17. December 30, 2018 Cadence Confidential: Cadence Internal Use Only