1. Department of Electronics Advanced Information Storage 17 Atsufumi Hirohata 17:00 02/December/2013 Monday (AEW 105)

2. Quick Review over the Last Lecture Cache and register : * http://withfriendship.com/user/levis/processor-register.php Cache to overcome the von Neumann bottleneck : Access speed : Processor memories

3. 17 Other Memory Concepts Millipede Nano-RAM Floating junction gate Hybrid memory cube I / O interfaces

4. Millipede Memory * http://www.ieeeghn.org/wiki/index.php/IBMs_Millipede_Memory_Chip In 2002, Gerd Binnig (IBM) proposed a millipede memory : * Arrayed AFM tips (1,024) for read / write Bit to be recorded as a nanometre-sized indentation by a heated tip Bit to be erased by a heated tip Bit to be read by a tip

5. Further Improvement * http://nanotechweb.org/cws/article/tech/36334 In 2005, an improved millipede memory was announced : * 64 × 64 cantilever array 7 mm × 7 mm data sled 800 Gbit / inch 2 10 nm indented bits Theoretically > 1 Tbit / inch 2 ×Slow access speed ×Mechanical parts

6. Nano-RAM (NRAM) * http://www.wikipedia.org/ In 2001, Nantero was founded to fabricate nano-RAM (NRAM) : *

7. Floating Junction Gate Floating junction gate (FJG) random access memory was invented by Oriental Semiconductor in 2013 : * * http://www.wikipedia.org/

8. Hybrid Memory Cube Micron and Samsung formed consortium to develop a new 3D architecture : * * http://japanese.engadget.com/2013/04/03/dram-hmc-1-0/ 3D memory arrays TSV (through-Silicon via) Memory chip fabricated on an interface logic between a CPU / GPU and memory controller Large band width (interface speed : × 15 as compared with DDR3 Low power consumption : - 70 % as compared with DDR3 Area : - 90 % as compared with RDIMM

9. Electrically-Induced Phase Changes Universities of Chiba and Karlsruhe jointly demonstrated Fe atomic structures can be transformed between bcc and fcc by applying an electric field using a STM tip : * * http://archive.wiredvision.co.jp/blog/yamaji/201012/201012241431.html

10. Semiconducting Mechanical Resonator * http://archive.wiredvision.co.jp/blog/yamaji/201103/201103241931.html Electrode B Electrode C Electrode A Mechanical resonator Input B (frequency : f B ) NTT developed a mechanical resonator for logic circuits : * Input A (frequency : f A ) Electrical input Mechanical resonance Different electrical output 1 : resonance / 0 : no signal time Output A and B (f C ) Output A or B (f D ) 0.1 pW / resonator Low power consumption : Current CPU : ~ 10 W Resonator : ~ 10 μW

11. Logic Operations Logic operations : * * http://archive.wiredvision.co.jp/blog/yamaji/201103/201103241931.html Input : A and B Input : B Input : A Input : none Output Intensity Output Frequency

12. Quasi-Liquid Memory Gel / liquid memrister was demonstrated by North Carolina State University : * * H.-J. Koo et al., Adv. Mater. 23, 3559 (2011).

13. Categories of Input / Output Interfaces Memories engaging through input / output (I/O) interfaces can be categorised : * * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling Human readable : Suitable for communicating with the computer user Examples : printers, terminals, video display, keyboard, mouse Machine readable : Suitable for communicating with electronic equipment Examples : disk drives, USB keys, sensors, controllers Communications : Suitable for communicating with remote devices Examples : modems, digital line drivers

14. Organisation of I / O Functions I/O technologies can be categorised : * * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling Prorgrammed I/O : The processor issues an I/O command on behalf of a process to an I/O module. That process then becomes busy and waits for the operation to be completed before proceeding. Interrupt-driven I/O : The processor issues an I/O command on behalf of a process. If non-blocking – processor continues to execute instructions from the process that issued the I/O command. If blocking – the next instruction the processor executes is from the OS, which will put the current process in a blocked state and schedule another process. Direct memory access (DMA) : A DMA module controls the exchange of data between main memory and an I/O module.

15. Evolution of I / O Functions * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling 1 Processor directly controls a peripheral device 2 A controller or I/O module is added 3 Same configuration as step 2, but now interrupts are employed 4 The I/O module is given direct control of memory via DMA 5 The I/O module is enhanced to become a separate processor, with a specialized instruction set tailored for I/O 6 The I/O module has a local memory of its own and is, in fact, a computer in its own right

16. DMA Alternative Configurations * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling

17. Model of I / O Organisations * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling

18. Buffering * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling Buffering is used to smooth out peaks in I/O requests : * Block-oriented devices : Stores information in blocks that are usually of fixed size Transfers are made one block at a time Possible to reference data by its block number Disks and USB keys are examples Stream-oriented devices : Transfers data in and out as a stream of bytes No block structure Terminals, printers, communications ports, and most other devices that are not secondary storage are examples

19. Types of Buffering * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling Without buffering, an operating system (OS) directly sees the device : * Single buffer, the OS assigns the buffer in a main memory for I/O requests : *

20. Timing of I / O Requests * http://www.docstoc.com/docs/120963914/Chapter-11-IO-Management-and-Disk-Scheduling Typical I/O transfer depends on : *