Presentation is loading. Please wait.

Presentation is loading. Please wait.

Relocation of an Admitted Process Requires Execution Time Binding

Similar presentations

Presentation on theme: "Relocation of an Admitted Process Requires Execution Time Binding"— Presentation transcript:

1 Relocation of an Admitted Process Requires Execution Time Binding
memory management unit (MMU) main memory LA PA + base address CPU The problem with contiguous memory management, of course, is external fragmentation, whose severity can be delayed by various means but can’t ultimately be fixed without compaction – unless you consider rebooting the system to be an acceptable fix, which most users and OS designers don’t And compaction: Is time consuming Requires the execution time relocation of already loaded processes, which means that load time binding is out, the hardware will have to have an MMU capable of execution time binding The second problem – an MMU that does execution time binding of a contiguous process – is not all that difficult or expensive to solve: All that’s necessary is a single base (or relocation) register in an MMU so that for the running process, every logical address emitted by the CPU is added to the base register to produce a physical address But the time involved in moving everybody around to compact the holes/fragments remains an issue for real-time systems The Base Address Register, sometimes known, for obvious reasons, as the Relocation Register, is part of the context of the running process

2 A Limit Register is Usually Added to Provide Increased Security
memory management unit (MMU) LA < limit ? size limit yes no address violation trap base address main memory CPU LA PA + A limit register, containing the size limit established when the process is admitted, can be used to prevent a process from accessing memory beyond its limit

3 Roadmap Paged memory management Motivation and overview
Contiguous memory management and its limitations Paged memory management Motivation and overview Binding, the page table, and the MMU Segmented memory management The segment table

4 Introduction to Paged Memory Management
frame # 0x0000 0x1000 0x2000 0x3000 0x4000 0x5000 0x6000 0x7000 0x8000 0x9000 0xa000 0xb000 address Pages are real enough, the loader does indeed chop the load module’s logical address space up into pages as it loads it from disk into memory Frames are a fiction, however, merely a consequence of the way the OS allocates physical memory – the memory itself knows nothing about frames and there are no changes to the memory hardware itself The loader just makes sure that whenever it loads a page, it loads it starting at a base address that is some multiple of the page/frame size ‒ i.e., the base address of frame #k is k*f, where f is the page/frame size, so the frame number is in fact nothing more than the most significant bits of its base address 1 2 3 4 5 6 7 8 9 a b By dividing the logical address space of the load module up into fixed length chunks called pages, paged memory management drops the need for managing variable length holes in memory, which is what leads to external fragmentation Pages are independently loading them into “frames” defined by evenly spaced main memory addresses that appear to divide memory into fixed length chunks exactly the same size as pages Any page can go to any frame Here, for example, we see the OS view of memory for a page/frame size of 212 = 163 bytes The physical memory doesn’t see any of this; it just continues its boring life of receiving a physical address plus a control bit which tells it whether to read or write that address It’s up to the loader to load pages into the correct physical addresses and it’s up to the MMU to properly bind a logical address to a physical address before it’s sent to the memory (we’ll see how shortly) page0 page1 page2 page3 load module main memory

5 The Long Term Scheduler, Admission, the Free Frame List, and the Page Table
The long term scheduler (in charge of admission) asks the memory manager if there are enough free frames on the free frame list for the new process If so, the requisite number of frames are removed from the FFL and inserted into the new process’s page table FFL For paged memory management, the free space list is simplified to a free frame list (FFL) whose management is much simpler than the older free space list: It doesn’t need to be ordered Since they’re fixed length, any frame is as good as any other for any use whatsoever Remember: All this number means in the FFL is that the physical memory from address 220*(pageSize) to address 221*(pageSize) is currently not used so it’s free for assignment to any page of any process that needs it 220 3e8 The page table (PT) is a data structure used for the execution time binding of paged memory management Each process must have its own page table A PT contains the frame numbers assigned to (containing) the process A process’s page table is created when it (a new process) is admitted and loaded 99 a2 Page Table (PT) 2f5 aa5 678 27 27b

6 Execution Time Binding for Paged Memory Management
memory management unit (MMU) main memory CPU LA PA p d d fp page p frame fp d PA=fp*(pageFrameSize)+d page table (PT) f0 f1 f2 fp The frame number the MMU finds there, in PT[p], is the frame in main memory that the OS assigned to hold page p of the process’s logical address space The MMU then appends the displacement from the logical address to the frame number and the result is the physical address to be sent to main memory p is used as an offset into the page table p The MMU circuitry splits up the logical address into a page number, p, and the displacement from the beginning of that page, d The memory management unit (MMU) uses the page table to bind each logical address emitted by the CPU to the correct physical address in main memory

7 So Where is the Page Table?
Page Table in the MMU Each page register also needs an extra bit to indicate whether or not it is valid So, for example, for a process whose logical address space was only 5 pages, only the first 5 page registers would be marked valid A CPU reference to an invalid page would cause the MMU to generate a hardware trap and the OS would terminate the process memory management unit (MMU) Since the total number of bits in a logical address is fixed, fewer bits for the page number, p, meaning a smaller maximum size for a page table, means faster context switch times, but it also means more bits for the displacement, d, which increases the page size As the page size grows larger, internal fragmentation becomes more of a concern main memory n bits CPU LA dp fp PA p d page table (PT) page registers If the page table for the running process is going to be in the MMU, it must be read in to what are called the MMU page registers as part of the context switch whenever the process is dispatched The bigger the page table, the longer the context switch time v i 2n page registers fp When a process is not running, its page table is kept in memory There are two possibilities for how the MMU will access the page table for a currently running process: Copy it into the MMU as part of the context switch Use the one in main memory There are advantages and disadvantages to each choice

8 Page Table Only in Main Memory memory management unit (MMU)
A page table limit register (PTLR) in the MMU can be used to avoid (fairly obvious) problems with keeping a valid/invalid bit with each page table entry in memory The PTLR and the PTBR are both part of a process’s context To find the physical address in memory of the desired entry in the page table, the page number is simply added to the PTBR main memory n bits CPU LA PA p d fp d yes no trap to OS ? p ≤ PTLR PTLR Page Table PTBR p max size n entries p + Note that using p as an offset in main memory means that the page table must be contiguous in memory If the largest possible page table fits into a single frame, that’s guaranteed, of course, since memory within a frame is contiguous Otherwise, it will be necessary to page the page table! fp If the MMU doesn’t have page registers, it will need to access the page table in memory and so will need a special purpose register called the page table base register to contain the base address of the page table for the running process (each process has its own page table, remember) One PTBR is faster to context switch than a whole bunch of page registers Note also that now every memory request by the CPU results in two physical memory references, the first into the page table to obtain fp for binding, and the second to actually satisfy the CPU’s request The result is to effectively double the time it takes to satisfy the CPU’s memory request The frame number there in PT[p] is then read into the MMU and concatenated with the displacement to complete the binding

9 Translation Look Aside Buffer (TLAB) memory management unit (MMU)
main memory CPU LA dp fp PA p dp yes no trap to OS ? p ≤ PTLR PTLR page table PTBR p + fp TLAB miss page # frame # TLAB TLAB hit A translation look aside buffer (TLAB) in the MMU can speed things up by eliminating the binding access(es) to physical memory most of the time The TLAB is an associative cache of recently referenced page numbers and their corresponding frame numbers When a page number is presented to the TLAB, it is searched associatively and if there’s a hit (the presented page number is found), its frame number is available for binding without the necessity of retrieving it from memory In the event the page number is not found (TLAB miss), the required frame number is retrieved from the page table in memory as before

10 pages in the contiguous logical address space
A Problem With Paging: Protection Bits Cannot Really be Applied to Pages The CPU can read data from here, but can’t write to it ‒ this might be a frame shared by some other process that owns the data, wants to share it, but doesn’t want it altered by this process Remember, each process has its own page table, so to share memory, the same frame number can appear in the page table of multiple processes  and will usually be in different pages in the different processes, each with its own protection bits read write execute PT From an MMU design standpoint, it’s easy enough: just add protection bits to each entry in the page table But the program’s logical address space as produced by the compiler is contiguous and the boundaries between the various code and data structures usually won’t fall neatly on page boundaries that the compiler doesn’t know anything about Data stored here can be both read and written by this process This page looks like it contains code; the CPU can fetch instructions from here for execution, but other accesses are not permitted code data pages in the contiguous logical address space read write execute ? ? ? The page table, can, in theory, help an OS to enforce a security policy so that, for example, users don’t try to overwrite code in library files that they in fact have a right to execute (but not to change) What protection should be applied to this page?

11 Roadmap Segmented memory management Motivation and overview
Contiguous memory management and its limitations Paged memory management Segmented memory management Motivation and overview The segment table

12 Segmented Memory Management
Segments are logically distinct chunks of the overall logical address space of a process Each segment is logically contiguous and is assigned (bound) to physical memory by the OS and the MMU independently of other segments user code library code shared memory stack global data heap process

13 memory management unit (MMU)
The Segment Table The segment number, s, is used as an offset into the segment table Depending on where the segment table is stored (same choices as for a page table), the MMU can use either a valid/invalid bit for each segment register or a segment table limit register (STLR) to determine if the segment number from a logical address is valid, just as was done for the page number by a paging MMU If the segment number is invalid, the MMU raises a segmentation error trap to OS To complete the binding, the displacement is added to the base address of the segment main memory memory management unit (MMU) CPU LA For a valid segment, the protection bits are then checked to determine if the operation requested by the CPU is legal for that segment If not, the MMU raises a protection violation trap ds< limit ? no segmentation error, core dumped yes The segment table is the key data structure used by segmented memory management, analogous to the page table for paged memory managmement It is where the protection bits applicable to each segment are stored – in fact, that’s one indicator of a segment: Something that is coherent in terms of its protection requirements and independent of other segments’ protection requirements n bits We didn’t need to do this check when paging, since all pages were the same size and all possible values of dp were always legal, but segments are variable length so a given segment may, and in general will, be less than the maximum possible segment size of 2n bytes, where n is the number of bits for the ds field of the logical address s ds + ds PA The MMU splits up the logical address it receives from the CPU into two fields: a segment number and a displacement within that segment segment table r w e segment base protection size address bits The displacement within the segment, ds, is then checked against the size limit of the segment from the segment table Each entry in the segment table records the protection bits, size, and base address for a segment Note that this binding mechanism means that a segment must be stored contiguously in main memory! That’s not progress; we’re back to contiguous memory management and external fragmentation again! ? ds

14 Paging Within a Segment Gets the Best of Both Worlds
The MMU checks for protection and segment size violations as before memory management unit (MMU) Each segment has its own page table main memory s ds < limit ? no segmentation error, core dumped yes paging using p, dp, and the segment’s page table, PTs PA CPU LA ds p dp PTs If the segment table were stored in memory – as opposed to segment registers in the MMU – the CPU’s requested memory operation would take 3 accesses to physical memory: One to retrieve the segment table entry for segment #s One to retrieve the page table entry for page p of segment s The access to the final, bound physical address A TLAB would be essentially mandatory here The only change to the segment table is that the base address is now for the segment’s page table, not for the segment itself Once the legality of the logical address and the CPU’s requested operation are determined, the displacement within segment, ds, is then split into two fields, a page number within the segment and a displacement within the page Binding is then completed via the segment’s page table segment table protection segment page table bits size base address

Download ppt "Relocation of an Admitted Process Requires Execution Time Binding"

Similar presentations

Ads by Google