SoC Testing 강성호 (연세대학교, 전기전자공학과) Copyrightⓒ2003.

목 차 Introduction Fault Modeling Fault Simulation
Automatic Test Pattern Generation IDDQ Testing Delay Testing Memory Testing IEEE P1500 Summary Copyrightⓒ2003

Boundary Scan TAP Controller
SoC Design Evolution Emergence of very large transistor counts on a single chip Mixed technologies on the same chip Creation of Intellectual Property (IP) Reusable IP-based design Data Path CPU Core DSP Core DRAM IP Core ROM UDL Logic BIST Memory BIST` Test Access Boundary Scan TAP Controller IO Pad 그림 바꿀 것. 단 그림은 evolution의 내용을 포함하여야 한다. Copyrightⓒ2003

SoC Test Challenges System integrator may have very limited knowledge of the adopted core Core provider may not know which test method, what types of faults, and what level of fault coverage to use Test of the embedded IP core is the joint responsibility of both core provider and system integrator Deeply embedded cores limit access to core port Mixed Technologies Logic, analog, memory The basic requirement is that test must not slow down overall growth of semiconductor and computing industries Copyrightⓒ2003

Mission of SoC Testing Efficient SoC test methodologies Y : Yield
Reduce manufacturing costs Reduce time-to-market Improve yield Y : Yield DL: Defect Level d : defect coverage DL = 1 - Y 1-d 초고집적 회로 설계 기술의 발전과 설계 자동화 기술의 발전, 반도체 재료 기술의 발전, 그리고 초미세 선폭 공정기술의 발전은 동일한 면적에 점점 더 많은 트랜지스터를 이용하여 시스템 설계를 하는 것을 가능하게 하였습니다. 여기에 다기능, 소형화, 저비용, 고신뢰 성을 갖는 제품을 원하는 소비자들의 기호는 기존에 보드에 구성되는 시스템을 하나의 칩에 구현할 수 있게 하였고, 이를 시스템 온 칩이라 합니다. 시스템 온 칩을 가능하게 하는 기술 중에 테스트 기술은 그 무엇보다도 중요하다고 할 수 있습니다. SIA NTRS’99에 의한 자료를 보면 전체 시스템 온 칩의 개발 시간에서 시스템 온 칩의 테스트 구조를 개발하는데 소요되는 시간이 30%를 차지하고 또 제조 비용에 있어서도 테스트에 소요되는 비용이 전체 시스템 온 칩의 개발 비용에서 50%차지하는 것만 보더라도 시스템 온 칩의 요소 기술 중에 테스트가 얼마나 큰 비중을 차지하는 지 알 수 있습니다. 시스템 온 칩의 목적 중에 하나가 짧은 시장 진입 시간이라는 점을 고려해 볼 때, 효과적으로 시스템 온 칩을 테스트 할 수 있는 표준적인 수단이 마련 되어야 함을 알 수 있습니다. Copyrightⓒ2003

PCB Test VS. SoC Test PCB test System-on-Chip test
IC Design ASIC Design Core Design UDL Design IC Manufacturing ASIC Manufacturing IC Test ASIC Test SOB Design SOC Integration SOB Manufacturing SOC Manufacturing SOB Test SOC Test PCB Manuf. Process SoC Manuf. Process PCB test Test is performed at multi-stages System-on-Chip test Test is performed at once 시스템 온 칩이 갖는 테스트상의 특징은 전통적인 시스템 온 보드의 제조 공정과 시스템 온 칩의 제조 공정의 비교에서 찾아 볼 수 있습니다. 우선 시스템 온 보드의 제조 공정은 그림에서 보는 바와 같이 그 제조 공정이 다단계로 구성이 되어 있기 때문에 테스트에 있어서도 다단계의 테스트가 적용됩니다. 즉 모든 소자들은 일단 보드에 집적되기 전에 제조 후 테스트의 과정을 거칩니다. 그러므로 시스템을 테스트 할 때는 개별 기능 블록인 소자에는 고장이 없다고 가정이 가능하고 개별 소자간의 상호 연결선의 테스트로 그 과정이 집중될 수 있습니다. 그러나 시스템 온 칩의 제조 공정에서 실질적으로 물리적인 제조는 단 한번에 이루어지므로 테스트의 과정은 분리될 수 없고 한번에 모든 테스트를 실시해야 합니다. 비록 설계는 코어 제공자에 의해서 미리 진행되지만 코어 사용자에게 건네어지는 설계물은 기술단계의 것일 뿐이고 아직 물리적인 제조를 하지 않았으므로 테스트는 진행될 수 없기 때문입니다. 그러므로 시스템 온 칩의 테스트는 코어간의 상호 연결선 뿐만이 아니라, 코어 내부의 테스트도 중요한 의미를 갖습니다. 이것이 시스템 온 칩의 테스트에 소요되는 시간을 증가시키는 원인이 되기도 합니다. Copyrightⓒ2003

Contents Fault Modeling Introduction Fault Simulation

Fault modeling Fault model Advantages of Modeling
Represent the effect of physical defects Advantages of Modeling The problem of fault analysis is a logical problem Complexity is reduced Technology-independent Tests derived for logical faults are valid for physical faults Single fault assumption Assume that there is at most one logical fault in the system justified by frequency testing strategy In most cases, a multiple fault can be detected by the tests designed for the individual single faults that compose the multiple one Copyrightⓒ2003

Logical Fault Models Gate level faults Transistor level faults
stuck-at short between signal and ground or power Bridging Short between two signals Transistor level faults Short Connecting points not intended to be connected Open (break) Breaking a connection Stuck-on (stuck-short) Stuck-open (stuck-off) Delay faults Temporary faults Copyrightⓒ2003

Stuck-at Fault Models Stuck-at-1 Stuck-at-0
Faulty line permanently set to 1 Stuck-at-0 Faulty line permanently set to 0 Fault can be at an input or output of a gate Single stuck at faults The number of stuck at faults is 2N where N is the number of fault sites Reasons why widely used Represents many different physical faults Independent of technology Tests that detect stuck faults detect other faults well The number of faults is small Can be used to model other type of faults Copyrightⓒ2003

Delay Fault Models Delay faults Two types of delay faults
Chip with timing-related defects May pass stuck-at fault testing, but fail when tested at-speed Two types of delay faults Gate delay fault Path delay fault <Gate delay fault> <Path delay fault> Copyrightⓒ2003

Contents Fault Simulation Introduction Fault Modeling

Fault Simulation Fault simulation Evaluating Test Vectors
Generating Tests Constructing Fault Dictionaries Analyzing Circuits under Presence of Faults Copyrightⓒ2003

Basic Fault Simulation
Fault Specification The total set of faults to be considered is determined Fault insertion The fault free network is transformed into a network which contains a physical defect or fault Fault Propagation Fault Detection A fault simulation system must have the ability to determine when a fault has become observable at some given point or primary output of the object network Post Processing (a) Fault is propagated (b) Fault is propagated through multiple paths (c) Fault is blocked Copyrightⓒ2003

Parallel Fault Simulation
A good circuit and w faulty circuits are simulated simultaneously passes are required where w is the number of bits of the host machine Example Three faults : B/1, F/0, and J/0 Bit-space : , FF = Fault-free J/0 B/1 F/0 FF Copyrightⓒ2003

Concurrent Fault Simulation
Simulates good circuit and simulates only faulty circuits that are different from the one in good circuit Faster than parallel fault simulation Lots of memory required Copyrightⓒ2003

PPSPF Parallel pattern single fault propagation Simple and efficient
Fails to consider the timing environment Since it does not work like event driven simulation, it is limited to devices which are combinational Copyrightⓒ2003

Contents Automatic Test Pattern Generation Introduction Fault Modeling
Fault Simulation Automatic Test Pattern Generation IDDQ Testing Delay Testing Memory Testing IEEE P1500 Summary Copyrightⓒ2003

Test Pattern Generation
Test generation Manual generation Pseudo random generation Algorithmic (or deterministic) test generation Automatic Test Pattern Generation (ATPG) Calculate the set of test patterns from a description of the logic network and a set of assumptions called fault models Copyrightⓒ2003

Automatic Test Pattern Generation
Result of ATPG Find a test pattern Redundant fault Run out of time/memory (Aborted fault) Cost of ATPG Low CPU time Quality of the generated tests High fault coverage Cost of Applying Test Small number of tests Fault Coverage # of detected faults / # of faults # of detected faults / (# of faults - # of redundant faults) (# of detected faults + # of redundant faults) / # of faults Copyrightⓒ2003

Definition Fault Excitation Fault Propagation Implication
The process of finding a sufficient set of PI values to cause the fault site in the good circuit to have a value opposite to the faulty value Fault Propagation The process of moving the effect of a fault closer to a PO Implication The process of determining the unique values implied by already assigned values The process can cause both forward and backward assignment of values Copyrightⓒ2003

Definition Reconvergent fan-out Line Justification Backtracking
A fan-out node, two or more of whose branches eventually are used as inputs to the same element The element at which the branch reconverted is called the point of reconvergence Line Justification The process of finding a set of PI values which cause the line to achieve the desired value Essentially the same as back drive with conflict resolution Backtracking Retracing in the search space to resolve the conflict by trying alternate assignments at previously assigned nodes Should store previously determined values Copyrightⓒ2003

General Outline of ATPG
Choose a fault if imply-and-check() = FAILURE return FAILURE if fault effect at PO and all lines are justified return SUCCESS if no fault effect can be propagated to a PO select an unsolved problem repeat select one untried way to solve it if solve( ) = success until all ways to solve it have been tried Copyrightⓒ2003

PODEM Path Oriented DEcision Making Search space on PIs
Implicit space enumeration Algorithm PODEM() if (Error at PO) return SUCCESS if (test not possible) return FAILURE get an objective backtrace the objective to PI imply the PI value if PODEM() == SUCCESS imply PI with X value assume target fault is I s-a-v objective() if ( the value of I is X ) return (I, v’) select a gate(G) from the D frontier select an input j of G with value X c = controlling value of G return ( j, c’) Copyrightⓒ2003

FAN FANout Oriented ATPG
Stop the back trace at a headline and postpone the line justification for the headline to the last Multiple back trace Free line Gate output whose predecessors are fanout free Head line Free line that enters a region of reconvergent fanout Copyrightⓒ2003

SOCRATES Goals Goals achieved by
SOCRATES is a direct descendant of FAN with improved implication procedure, improved unique sensitization procedure, and improved multiple backtracing procedure Goals (1) minimizing the unidentified non-solution area, and (2) avoiding all non-solution areas during the search process Goals achieved by (1) optimize the pruning of the search space (2) reduce the number of backtrackings (3) recognize conflicts as early as possible (4) avoid useless backtracking in unidentified nonsolution areas Copyrightⓒ2003

Sequential Circuit ATPG
Sequential ATPG is more complex than combinational ATPG due to signal dependencies across frames Sequential circuit test generation problems Memory states are usually unknown upon power-up Need initialization sequence Memory states cannot be observed directly Long test sequence Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Copyrightⓒ2003

Sequential Circuit ATPG
Time frame expansion If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame -1 -n+1 Unknown or given Init. state Vector 0 Vector -1 Vector -n+1 PO 0 PO -1 PO -n+1 State variables Next state Copyrightⓒ2003

Contents IDDQ Testing Introduction Fault Modeling Fault Simulation

What is IDDQ? IDDQ Testing : Detecting faults by monitoring IDDQ
IDDQ is the IEEE symbol for the quiescent power supply current in an MOS circuit. In our cases we are referring to IDDQ in CMOS ICs Perfect CMOS circuits have IDDQ values typically less than 100 nA There is no direct conducting path between Vdd and Vss Most CMOS IC defects elevate IDDQ several orders of magnitude greater than non-defective circuit IDDQ Testing is the most sensitive way to detect the majority of CMOS defects Voltage testing based on stuck-at fault model cannot fully detect transistor level defects (about 40 %) Delay fault is a defect which make a circuit malfunction at desired clock rates or not meet timing specification. Delay testing checks if delay faults exist in a circuits or not. To detect delay faults, a two-pattern test is needed during two clock cycles. There are various types of delay testing according to the hardware models. Copyrightⓒ2003

High IDDQ Indicates a Defective IC
When CMOS is not actually switching, one transistor in CMOS pair is always off Draws only a leakage current on the order of nA IDDQ can become as high as several mA Copyrightⓒ2003

Advantages of IDDQ Testing
Direct Observability >>50% of transistors tested with only a few vectors Detection of defects that do not cause functional failure Identification of subtle defects and failure mechanisms in addition to those that affect logic functions Greatly increased detection of common physical defects Gate oxide shorts, Interconnect shorts, Interconnect opens 100% coverage of stuck-at faults for many designs Reduced test vector count Simplified test vector generation and fault simulation No additional on-chip circuitry required Copyrightⓒ2003

Current monitoring Techniques
ATE ATE Current Supply Monitor BICS DUT DUT CUT The most important work in IDDQ testing may be the design of current sensors. There exist three methods. External Monitoring Test Fixture Built-In Current Sensor Copyrightⓒ2003

Contents Delay Testing Introduction Fault Modeling Fault Simulation

Delay Testing Checks if a circuit has delay faults or not
Determines input patterns to be applied to detect and locate delay defects Requires at least two clock cycles Various types according to hardware models Input Output Inputs Combinational Outputs Latches Circuits Latches Input Clock Output Clock Input Clock Sampling Clock Tc t0 t1 t2 V1 V2 outputs applied applied sampled Copyrightⓒ2003

Delay Fault Model Gate delay fault model Path delay fault model
Localized defects only The number of faults is proportional to the number of inputs and outputs of gates Cannot test distributed delay defects Easy to test All possible single GDF can be considered Path delay fault model Can test both lumped & distributed defects Effective in statistical design philosophy Large number of paths <Gate delay fault model> <Path delay fault model> Copyrightⓒ2003

Types of Path Delay Tests
Hazard Free Robust Test Guarantees the signals on the path are free from dynamic hazards Guarantees to detect the delay defects independent of the delays in other circuits Robust Test Non-Robust Test Guarantees to detect the delay defects if all off-path inputs reach their final values prior to the on-path transition Copyrightⓒ2003

Local Requirements of Tests
Hazard Free Robust Hazard free constant values for all off path inputs Robust First vector : On-path elements must have initial values according to the specified transition types Second vector : On-path elements must have final values due to the on-path fanin values Non Robust First vector : The first element on the path must have initial values according to the specified transition types Copyrightⓒ2003

Robust Test Test for falling transition through path P3: Steps A through E Place F0 at path origin Propagate F0 through OR gate; also propagates as R1 through NOT gate F0 interpreted as U0; propagates through AND gate Change off-path input to S0 to Propagate R1 through OR gate Set input of AND gate to S0 to justify S0 at output E S0 U0 XX S0 D U0 C A R1 F0 Path P3 XX F0 R1 U0 Robust Test: S0, F0, U0 B Copyrightⓒ2003

Non-Robust Test Rising transition through path P2 has no robust test
Place R1 at path origin Propagate R1 through OR gate; interpreted as U1 on off-path signal; propagates as U0 through NOT gate Set input of AND gate to propagate R1 to output R1 non-robustly propagates through OR gate since off-path input is not S0 C D XX U1 R1 R1 A Path P2 U1 R1 R1 U1 U0 XX U0 Non-robust test requires Static sensitization: S0=U0, S1=U1 Non-robust test: U1, R1, U0 B Copyrightⓒ2003

Delay Test Generation Algorithm
Copyrightⓒ2003

Contents Memory Testing Introduction Fault Modeling Fault Simulation

Memory Testing Memory testing is difficult Problems
Introduction Memory Testing Memory testing is difficult Exponential increase in the number of bits Exponential increase in density Memory cells are placed closely together More sensitive to influence of neighborhood cells Problems Not based on specific fault model Time complexity : O(n log n) Larger memory requires excessive test time Expensive test cost Copyrightⓒ2003

Functional Fault Models
Address decoder fault : AF Stuck-at fault : SAF Stuck-open fault : SOF Transition fault : TF A cell fails to make 1→0→1 transition A cell fails to make 0→1→0 transition Coupling fault : CF A write operation which generates transition in one cell, changes the contents of another cell Since it is impossible to consider all coupling faults, generally 2-coupling fault model is used Types State CF (CFst), Inversion CF (CFin), Idempotent CF (Cfid), Linked CF Pattern sensitive fault : PSF The contents of a cell can be influenced by the contents of all other cells in the memory PSF can be considered the most general case of the k-coupling faults Use neighborhood pattern sensitive faults (NPSF) Type-1 : 5-cell NPSF Model Type-2 : 9-cell NPSF Model Data retention fault : DRF Copyrightⓒ2003

March Test Algorithm Consist of march elements March Element
A finite sequence of operations Applied to every cell in memory before proceeding to the next cell Classification of March Test Copyrightⓒ2003

NPSF Test Algorithm Five-cell neighborhood test Active NPSF (ANPSF)
Write then read 16 patterns (all combinations) of 0’s and 1’s in the cells surrounding a single cell for all cells for all addresses Intent is to detect cell pattern sensitivity Long test sequence Active NPSF (ANPSF) The base cell is forced to have certain value by the contents of its deleted neighborhood Passive NPSF (PNPSF) The base cell cannot be changed due to a certain pattern in the deleted neighborhood Static NPSF (SNPSF) The base cell changes its contents due to changes in the pattern of the deleted neighborhood B : Base Cell E(d1) : East Neighborhood Cell W(d2) : West Neighborhood Cell S(d3) : South Neighborhood Cell N(d4) : North Neighborhood Cell Copyrightⓒ2003

Contents IEEE P1500 Introduction Fault Modeling Fault Simulation

IEEE P1500 Goals of IEEE P1500 Scope of IEEE P1500
Standardize a Core Test Architecture which : Defines a core test interface between an embedded core and the system chip Facilitate test reuse for embedded cores through core access and isolation mechanisms, and provide testability for system chip interconnect and logic Facilitates core test interoperability, with plug-and-play protocols, in order to improve the efficiency of test between core providers and core users Scope of IEEE P1500 Standardize core test mechanisms, for core access and isolation, including protocols and test mode control System Chip test access mechanism is defined by the system chip integrator The Core test method is defined by the core provider – P1500 supports, and enables, various different methods(e.g., scan, BIST, Iddq, etc,) Copyrightⓒ2003

System Chip with P1500 Wrapped Cores
TAM-Source User Defined Test Access Mechanism TAM-Sink TAM-In TAM-Out TAM-In TAM-Out Standard P1500 Standard P1500 Chip Inputs Core 1 Core N Chip Outputs WSO1 WSIN Core Test Wrapper Core Test Wrapper WSI1 Wrapper control WSON P1500 WIP System Chip TAM Source/Sink From chip I/O, test bus/rail/port, BIST, etc.. TAM In/Out 0 to n lines for parallel and/or serial test data, or test control P1500 Wrapper Interface Port(WIP) From chip-level TAP controller, chip I/0, … Copyrightⓒ2003

P1500 Architecture Components
Core Wrapper Interface Port(WIP) Wrapper Serial Input(WSI) Wrapper Serial Output(WSO) Wrapper Instruction Register(WIR) Wrapper Cells from the Wrapper Boundary Register (WBR) TAM-IN TAM-Out Wrapper Wrapper Bypass Register P1500 Wrapper : WIR for loading wrapper instruction WBR with Wrapper Cells at each terminal A Bypass register for the SIL WIP for control of Wrapper Register via SIL May also provide controls for PIL/TAM Copyrightⓒ2003

P1500 Wrapper Interface Port(WIP)
Core WRSTN UpdateWR ShiftWR CaptureWR SelectWIR WRCK WSI Wrapper WSO WIP Controls & Clock The WIP is used to access the WIR, Bypass & other data registers via the SIL WIP Termianls : WRCK is the wrapper clock Dedicated for WIR and BYPASS, WBR may also ue “auxiliary” clock(s) WRSTN is an asynchronous Wrapper Reset SelectWIR selects whether the WIR or DR(s) is connected between WSI and WSO UpdateWR, ShiftWR and CaptureWR are enables for register operations May be used for gating WRCK clock internal to Wrapper Copyrightⓒ2003

P1500 Wrapper Boundary Cells
Core Bypass WIR Wrapper Boundary Register WSI WIP Controls & Clock WSO Wrapper Boundary Cells Wrapper Boundary Cells are required on all functional core terminals Wrapper Boundary Cells are not required on Test terminals or “Special Case” terminals, such as analog Copyrightⓒ2003

Wrapper Cell Model CTO CTI CFI CFO Cell Functional Input Cell Test Output Cell Functional Output Cell Test Input Cell Modes Normal : No Effect, core functions normally Inward Facing: Affects the core, test is directed towards core Outward Facing: Affects the core, test is directed outward from core Safe: Affects the core & ensures wrapper does not damage core or system ( a recommended mode) Note: Inward and Outward Facing Test Modes Mirror one another Copyrightⓒ2003

Wrapper Cell Model CTO CTI CFI CFO Cell Functional Input Cell Test Output Cell Functional Output Cell Test Input Cell Events Shift: Move data through shift path Capture : Sample data Apply : Moment when test data becoms active and effective Update: type Update Transfer: Move data from Update element to Shift path Copyrightⓒ2003

SoC SIL Connection Example
Core 1 Core 2 Core n WSI1 WSI2 WSIn WSO1 WSO2 WSOn SelectWIR WRCK WRSTN CaptureWR ShiftWR UpdateWR System Chip Serial connection of SILS: SelectWIR must be common to all core Recommended that other WIP signals Copyrightⓒ2003

SoC SIL Connection Example
Core3 Core4 Core1 WSI1 Core2 SelectWIR WRCK WRSTN CaptureWR ShiftWR UpdateWR WSO1 WSI2 WSI3 WSO3 WSI4 WSO4 WSO2 System Chip Serial connection of SILs, Core 2 has child cores SelectWIR must be common to all cores Recommended that other WIP signals Many variations of SIL selection with Core2-Core3-Core4 Multiple-bit Bypass Register may be seen through Core2’s SIL Copyrightⓒ2003

SelectWIR WRCK WRSTN CaptureWR ShiftWR UpdateWR
SoC SIL Connection Example Core1 Core3 Core2 WSI1 WSO1 WSI3 WSI2 SelectWIR WRCK WRSTN CaptureWR ShiftWR UpdateWR WSO3 WSO2 System Chip Multiple/parallel SILs within SoC Multiple WIP “busses’ within System Chip Example where WIPs can be controlled separately via chip-level IEEE TAP Copyrightⓒ2003

P1500 Instructions Wrapper External Test (WEXTEST) – Mandatory Instruction To operate the wrapper to allow for external testing Wrapper Bypass (WBYPASS) – Mandatory Instruction To allow functional operation of the core through the wrapper Wrapper Clamp (WCLAMP) – Optional Instruction Wrapper preload (WPRELOAD) – Optional Instruction To allow setup for test Wrapper Safe State (SAFESTATE) – Optional Instruction To operate the wrapper such that it provides a safe mode for the core and if needed, the logic adjacent to the core(from the outputs of the core) Core Test (CORETEST) – Mandatory Instruction To operate the wrapper (and TAM) to allow for internal testing or debug Wrapper Serial Core Test (WSCORETEST) – Optional Instruction Serial Core Test (SCORETEST) – Optional Instruction To operate the wrapper to allow for debug or serial test Copyrightⓒ2003

Contents Summary Introduction Fault Modeling Fault Simulation

Summary Test Automation Fault simulation Testability measure
RF/Analog Core User Defined Core User Defined Core DRAM IP ROM UDL BIST Mem BIST Test Access SoC Test Controller IO Pad Low cost external ATE Memory test algorithm Memory BIST, BISR Testable design Analog Fault modeling Mixed signal Built-In Self Test Built-In Self Calibration Testable core design Logic BIST Test reuse Hierarchical testing Core access architecture Parallel access & bypass Core isolation IP-system test interface Test spec. Test hardware control Test scheduling Automatic test pattern Fault simulation Testability measure Scan insertion & synthesis BIST circuit synthesis Boundary scan insertion & synthesis Test Automation Copyrightⓒ2003

References M. Abramovich, M. A. Breuer, and A. D. Friendman, Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990. M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-signal VLSI Circuits, Kluwer Academic Publishers, Boston, 2000. T. L. Faulkner, C. W. Bartlett, and M. Small, “Hardware Design Faults: A Classification and Some Measurements,” ICL Technical Journal, pp , November, 1982. W. Maly, “Realistic Fault Modeling for VLSI Testing,” Proc. 24th ACM/IEEE Design Automation Conf., pp , 1987. M. Abramovici, Y. H. Levendel, and P. R. Menon, “A Logic Simulation Machine,” IEEE Trans. on Computer-Aided Design, Vol. CAD-2, No. 2, pp , April, 1983. V. D. Agrawal, A. K. Bose, P. Kozak, H. N. Nham, and E. Pacas-Skewes, “A Mixed-Mode Simulator,” Proc. 17th Design Automation Conf., pp , June, 1980. Copyrightⓒ2003

References S. B. Akers, “A Logic System for Fault Test Generation,” IEEE Trans. on Computers, Vol. C-25, No. 6, pp , June, 1976. H. Fujiwara and T. Shimono, “On the Acceleration of Test Generation Algorithms,” IEEE Trans. on Computers, Vol. C-32, No. 12, pp , December, 1983. J. J. Tang, K. J. Lee, and B. D. Liu, “A practical current sensing technique for IDDQ testing,” IEEE Trans. on Computer-Aided Design, vol. 3, No. 2, pp , June, 1995. Y. Miura and K. Kinoshita, “Circuit design for built-in current testing,” Proc. Intn’l. Test Conf., pp , Nov., 1992. S. Kang, O. Law and B. Underwood, “Path-Delay Fault Simulation for a Standard Scan Design Methodology”, Proc. Intn’l Conf. on Computer Design, pp , 1994. A. J. Van de Goor, Testing Semiconductor Memories, John Wiley & Sons, New York, 1991. P. Mazumder, Testing and Testable Design of High-Density Random-Access Memories, Kluwer Academic Publishers, Boston, 1996. IEEE P1500 Web Site, Copyrightⓒ2003

SoC Testing 강성호 (연세대학교, 전기전자공학과) Copyrightⓒ2003.

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