1. Chapter 7. Basic Processing Unit

2. Overview Instruction Set Processor (ISP) Central Processing Unit (CPU)
A typical computing task consists of a series of steps specified by a sequence of machine instructions that constitute a program.
An instruction is executed by carrying out a sequence of more rudimentary operations.

3. Some Fundamental Concepts

4. Fundamental Concepts
Processor fetches one instruction at a time and perform the operation specified.
Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered.
Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC).
Instruction Register (IR)

5. Executing an Instruction
Fetch the contents of the memory location pointed to by the PC. The contents of this location are loaded into the IR (fetch phase).
IR ← [[PC]]
Assuming that the memory is byte addressable, increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
Carry out the actions specified by the instruction in the IR (execution phase).

6. Processor Organization
MDR HAS TWO INPUTS AND TWO OUTPUTS
Datapath
Textbook Page 413

7. Executing an Instruction
Transfer a word of data from one processor register to another or to the ALU.
Perform an arithmetic or a logic operation and store the result in a processor register.
Fetch the contents of a given memory location and load them into a processor register.
Store a word of data from a processor register into a given memory location.

8. Register Transfers B A Z
ALU Y in
out R i b us
Internal processor
Constant 4
MUX
Figure Input and output gating for the registers in Figure 7.1.
Select

9. Figure 7.3. Input and output gating for one register bit.
Register Transfers
All operations and data transfers are controlled by the processor clock.
Figure Input and output gating for one register bit.

10. Performing an Arithmetic or Logic Operation
The ALU is a combinational circuit that has no internal storage.
ALU gets the two operands from MUX and bus. The result is temporarily stored in register Z.
What is the sequence of operations to add the contents of register R1 to those of R2 and store the result in R3?
R1out, Yin
R2out, SelectY, Add, Zin
Zout, R3in

11. Fetching a Word from Memory
Address into MAR; issue Read operation; data into MDR.
Figure Connection and control signals for register MDR.

12. Fetching a Word from Memory
The response time of each memory access varies (cache miss, memory-mapped I/O,…).
To accommodate this, the processor waits until it receives an indication that the requested operation has been completed (Memory-Function-Completed, MFC).
Move (R1), R2
MAR ← [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]

13. Timing MAR ← [R1] Assume MAR is always available on the address lines
of the memory bus.
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 ← [MDR]

14. STORING A WORD IN MEMORY
Desired Address is loaded into MAR.
Data to be written are loaded onto MDR.
Write command is issued.
Move R2,(R1)
R1out,MARin
R2out,MDRin,Write
MDRoutE,WMFC

15. Execution of a Complete Instruction
Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the memory location pointed to by R3)
Perform the addition
Load the result into R1

16. Architecture B A Z
ALU Y in
out R i b us
Internal processor
Constant 4
MUX
Figure Input and output gating for the registers in Figure 7.1.
Select

17. Execution of a Complete Instruction
Add (R3), R1

18. Execution of Branch Instructions
A branch instruction replaces the contents of PC with the branch target address, which is usually obtained by adding an offset X given in the branch instruction.
The offset X is usually the difference between the branch target address and the address immediately following the branch instruction.
Conditional branch

19. Execution of Branch Instructions
Step
Action 1 PC ,
MAR ,
Read,
Select4,
Add, Z
out in in 2 Z , PC , Y ,
WMF C
out in in 3
MDR , IR
out in 4
Offset-field-of-IR ,
Add, Z
out in 5 Z , PC ,
End
out in
Figure Control sequence for an unconditional branch instruction.

20. Conditional branch:
We check status of condition codes before loading new value into the PC.
Branch on negative(branch<0) instruction in step4 is replaced with
Offset-field-of-IRout, Add, Zin, if N=0 then End
Thus if N=0 processor returns to step1 after step4.
If N=1, step5 is performed to load new value into PC, thus performing branch operation.

21. Multiple-Bus Organization

22. Multiple-Bus Organization
Add R4, R5, R6
Step
Action 1 PC ,
R=B,
MAR ,
Read,
IncPC
out in 2
WMF C 3
MDR ,
R=B, IR
outB in 4 R4 , R5 ,
SelectA,
Add, R6 ,
End
outA
outB in
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.

23. Quiz What is the control sequence for execution of the instruction
Add R1, R2
including the instruction fetch phase? (Assume single bus architecture)

24. Hardwired Control

25. Overview
To execute instructions, the processor must have some means of generating the control signals needed in the proper sequence.
Two categories: hardwired control and microprogrammed control
Hardwired system can operate at high speed; but with little flexibility.

26. Control Unit Organization
CLK
Control step
Clock
counter
External
inputs
Decoder/ IR
encoder
Condition
codes
Control signals
Figure Control unit organization.

27. Detailed Block Description

28. Generating Zin Zin = T1 + T6 • ADD + T4 • BR + …
Branch
Add T T 4 6 T 1
Figure Generation of the Zin control signal for the processor in Figure 7.1.

29. Generating End
End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

30. A Complete Processor

31. Microprogrammed Control

32. Overview
Control signals are generated by a program similar to machine language programs.
Control Word (CW); microroutine; microinstruction

33. Overview

34. Control Word
Word whose individual bits represent various control signals.
Each of the control steps in control sequence of instruction defines unique combination of 1’s and 0’s in the CW
Select y--- select=0
Select 4----select=1
Sequence of CW’s corresponding to control sequence is microroutine.
Individual control words in microroutine is called microinstructions.

35. Microroutines for all instructions are stored in control store.
Control unit generates control sgls by sequentially reading CW’s from control store.
For sequential reading micro program counter is used.
Every time a new instruction is loaded into IR, the o/p of the block labeled starting address generator is loaded into microprogrammed counter (MPC).
MPC is then automatically incremented by clock causing successive microrutines to be read from control store.

36. Overview Control store One function cannot be carried
out by this simple
organization.

37. The previous organization cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to choose between alternative courses of action.
In hardwired control it is handled by logic function End=T7.ADD+T5.BR+(T5.N+T4.rev-N).BRN+…. In encoder circuitry.
In microprogram control , we use conditional branch microinstructions(specify branch address, external i/p,condition codes---to be checked as a condtion for branching to take place)

38. Use conditional branch microinstruction. After loading this into IR,
a branch microinstruction transfers control to corresponding microroutine
Which is assumed to start at 25 in control store.
This address is o/p of starting address generator.
Microinstruction at loc-25 test N bit. If N=0 branch to 0 to fetch new instruction. Otherwise loc-26 is executed to put branch address into reg-Z and then into PC
Address
Microinstruction PC ,
MAR ,
Read,
Select4,
Add, Z
out in in 1 Z , PC , Y ,
WMF C
out in in 2
MDR , IR
out in 3
Branch to
starting
address of
appropriate
microroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 If
N=0,
then
branch to
microinstruction 26
Offset-field-of-IR ,
SelectY,
Add, Z
out in 27 Z , PC ,
End
out in
Figure Microroutine for the instruction Branch<0.

39. Overview Figure 7.18. Organization of the control unit to allow
External
inputs
Starting and
Condition IR
branch address
codes
generator
Clock m P C
Control CW
store
Figure Organization of the control unit to allow
conditional branching in the microprogram.

40. Starting and Branch address generator block loads new address into MPC when microinstruction instructs it to do so.
I/P’s to this block are External i/p’s and CC,IR.
MPC is incremented every time a new microinstruction is fetched from microprogram memory except in following situations
When a new instruction is loaded into IR, MPC is loaded with starting address of micro-routine for that instruction
When Branch microinstruction is encountered and branch condition is satisfied, MPC is loaded with branch address.
When END microinstruction is encountered, MPC is loaded with address of 1st CW in microroutine-fetch cycle.

41. Microinstructions
A straightforward way to structure microinstructions is to assign one bit position to each control signal.
However, this is very inefficient.
The length can be reduced: most signals are not needed simultaneously, and many signals are mutually exclusive(gating contents of 2 reg to bus same time-not possible,read/write to memory at same time-not possible).
All mutually exclusive signals are placed in the same group in binary coding.
4 bits to represent 16 functions in ALU.
Reg-o/p control sgls-Pcout,MDRout,Zout, offsetout, R0out,R1out,R2out,R3out and TEMPout---placed in 1group…selected by 4bit code.

42. Partial Format for the Microinstructions
What is the price paid for
this scheme?

43. Further Improvement
Enumerate the patterns of required signals in all possible microinstructions. Each meaningful combination of active control signals can then be assigned a distinct code.
Vertical organization(highly encoded scheme)-slower operating speed.
Horizontal organization(minimally encoded scheme)-higher operating speed is desired

44. Microprogram Sequencing
If all microprograms require only straightforward sequential execution of microinstructions except for branches, letting a μPC governs the sequencing would be efficient.
However, two disadvantages:
Having a separate microroutine for each machine instruction results in a large total number of microinstructions and a large control store.
Longer execution time because it takes more time to carry out the required branches.
Example: Add src, Rdst
Four addressing modes: register, autoincrement, autodecrement, and indexed (with indirect forms).

45. - Bit-ORing
- Wide-Branch Addressing
- WMFC

46. Add src,Rdst
Source operand can be specified in any addressing mode: register,autoincrement,autodecrement and indexed as well as in indirect forms of 4 modes.
Each box represents microinstruction that controls transfers and operations indicated within box.
Microinstruction at address indicated by octal number above upper right hand corner of box.
Point labelled “alpha”—necessary to choose b/w actions required by direct and indirect addressing modes.
Indirect mode-microinstruction at 170 is performed to fetch operand from memory.
Direct mode-Loc-171 is performed.

47. Wide Branch Addressing
Wide branch occurs at 003.
Instruction decoder generates starting address of micro-routine loaded into IR.
Register IR contains ADD instruction, Instr-decoder generates microinstruction address 101. But it cannot be loaded into MPC.
Source operand of ADD can be specified in any addressing modes.
Bit OR-ing should change 101 to any one of 161,141,121,101,111 depending on addressing mode used in instruction.

48. Use of WMFC WMFC issued at 112—which causes branch to 171.
Combining 2opns introduces pblm.
WMFC may take several clk cycles to complete.
If branch allowed to happen at 1st clk cycle, microinstruction at 171 would be fetched and executed prematurely.
To avoid this pblm, branch must not take place until memory transfer in progress is completed.
WMFC sgl must inhibit any change in contents of MPC during waiting period.

49. Autoincrement mode-detailed examination
Add (Rsrc)+,Rdst
Instruction has 3 bit field to specify addressing mode for source operand.
Bit patterns 11,10,01,00 located in bits 10 and 9 denote indexed,autodecrement,autoincrement,
register mode.
Bit-8 specify indirect version.
Processor has 16 registers.(4 bit code)
Source operand is specified using mode field.
Register indicated by bits 7 thro 4.
Destination operand is in register(bits 3 thro 0)

50. 101 (from Instruction decoder);
Mode
Contents of IR
OP code 1
Rsrc
Rdst 11 10 8 7 4 3
Address
Microinstruction
(octal)
000 PC
, MAR
, Read, Select 4
, Add, Z
out in in
001 Z
, PC
, Y
, WMFC
out in in
002
MDR
, IR
out in
003 m
Branch { m PC
101 (from Instruction decoder); m PC
[IR ]; m PC
[IR ] ×
[IR ] ×
[IR ]}
5,4
10,9 3 10 9 8
121
Rsrc
, MAR
, Read, Select4, Add, Z
out in in
122 Z
, Rsrc
out in
123 m
Branch { m PC
170; m PC
[IR 8
]}, WMFC
170
MDR
, MAR
, Read, WMFC
out in
171
MDR
, Y
out in
172
Rdst
, SelectY
, Add, Z
out in
173 Z
, Rdst
, End
out in
Figure 7.21.
Microinstruction for Add (Rsrc)+,Rdst.
Note:
Microinstruction at location 170 is not executed for this addressing mode.

51. Microinstructions with Next-Address Field
The microprogram we discussed requires several branch microinstructions, which perform no useful operation in the datapath.
A powerful alternative approach is to include an address field as a part of every microinstruction to indicate the location of the next microinstruction to be fetched.
Pros: separate branch microinstructions are virtually eliminated; few limitations in assigning addresses to microinstructions.
Cons: additional bits for the address field (around 1/6)

52. Each instruction contains the address of the next instruction.
No need for a counter to keep track of sequential addresses.
MPC is replaced with a Microinstruction address register(MAR)
MAR is loaded from next address field in each microinstruction.
Next address bits are fed thro OR gates to MAR so that address can be modified on basis of data in IR,external i/ps and CC.
Decoding circuits generate the starting address of a given microroutine on basis of Opcode in IR.

53. Microinstructions with Next-Address Field

54. We need several control sgls that are not included in partial microinstruction format.
Instead of referring to R0 to R15, we use the names Rsrc and Rdst which can be decoded into actual control sgls with the data in src and dst fields of IR.
Bit ORing is needed in microinstruction 003 to determine address of next microinstruction basd on addressing mode(bits 8 to 10)
Here Ormode control---Oring
123,143,166—bit Oring is used to decide if indirect addressing is used.Here ORindsrc is used.

56. Implementation of the Microroutine

57. Revised routine has one less microinstruction.
Branch at 123 has been combined with microinstruction immediately preceding it.
When microinstruction sequencing is controlled by MPC,END sgl is used to reset MPC to point to starting address of microinstruction that fetches next machine instruction to be executed.
Here reseting not done by END sgl..instead specified explicitly in F0 field.

59. bit-ORing

60. Further Discussions
Prefetching
Emulation