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Krste Asanovic Electrical Engineering and Computer Sciences

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Presentation on theme: "Krste Asanovic Electrical Engineering and Computer Sciences"— Presentation transcript:

1 CS 152 Computer Architecture and Engineering Lecture 15 - Advanced Superscalars
Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley CS252 S05

2 Last time in Lecture 14 Control hazards are serious impediment to superscalar performance Dynamic branch predictors can be quite accurate (>95%) and avoid most control hazards Branch History Tables (BHTs) just predict direction (later in pipeline) Just need a few bits per entry (2 bits gives hysteresis) Need to decode instruction bits to determine whether this is a branch and what the target address is Branch Target Buffer (BTB) predicts whether a branch, and target address Needs PC tag, predicted Next-PC, and direction Just needs PC of instruction to predict target of branch (if any) Return address stack: special form of BTB used to predict subroutine return addresses 4/1/2008 CS152-Spring’08 CS252 S05

3 “Data in ROB” Design (HP PA8000, Pentium Pro, Core2Duo)
Register File holds only committed state Reorder buffer Load Unit FU Store < t, result > t1 t2 . tn Ins# use exec op p1 src1 p2 src2 pd dest data Commit On dispatch into ROB, ready sources can be in regfile or in ROB dest (copied into src1/src2 if ready before dispatch) On completion, write to dest field and broadcast to src fields. On issue, read from ROB src fields 4/1/2008 CS152-Spring’08 CS252 S05

4 Unified Physical Register File (MIPS R10K, Alpha 21264, Pentium 4)
Rename Table r ti r2 tj FU Store Unit < t, result > Load t1 t2 . tn Reg File Snapshots for mispredict recovery (ROB not shown) One regfile for both committed and speculative values (no data in ROB) During decode, instruction result allocated new physical register, source regs translated to physical regs through rename table Instruction reads data from regfile at start of execute (not in decode) Write-back updates reg. busy bits on instructions in ROB (assoc. search) Snapshots of rename table taken at every branch to recover mispredicts On exception, renaming undone in reverse order of issue (MIPS R10000) 4/1/2008 CS152-Spring’08 CS252 S05

5 Pipeline Design with Physical Regfile
Branch Resolution Update predictors Branch Prediction kill Out-of-Order In-Order PC Fetch Decode & Rename Reorder Buffer Commit In-Order Physical Reg. File Branch Unit ALU MEM Store Buffer D$ Execute 4/1/2008 CS152-Spring’08 CS252 S05

6 Lifetime of Physical Registers
Physical regfile holds committed and speculative values Physical registers decoupled from ROB entries (no data in ROB) ld r1, (r3) add r3, r1, #4 sub r6, r7, r9 add r3, r3, r6 ld r6, (r1) add r6, r6, r3 st r6, (r1) ld r6, (r11) ld P1, (Px) add P2, P1, #4 sub P3, Py, Pz add P4, P2, P3 ld P5, (P1) add P6, P5, P4 st P6, (P1) ld P7, (Pw) Rename When can we reuse a physical register? When next write of same architectural register commits 4/1/2008 CS152-Spring’08 CS252 S05

7 Physical Register Management
Rename Table Physical Regs Free List P0 P0 R5 P5 R6 P6 R7 R0 P8 R1 R2 P7 R3 R4 P1 P1 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P2 P3 P3 P2 P4 P4 <R6> P5 p <R7> P6 p <R3> P7 p <R1> P8 p Pn ROB (LPRd requires third read port on Rename Table for each instruction) op p1 PR1 p2 PR2 ex use Rd PRd LPRd 4/1/2008 CS152-Spring’08 CS252 S05

8 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p <R1> P8 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB x ld p P r P0 P8 4/1/2008 CS152-Spring’08 CS252 S05

9 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p <R1> P8 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 P1 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB x ld p P r P0 P8 x add P r P1 P7 4/1/2008 CS152-Spring’08 CS252 S05

10 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p <R1> P8 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 P1 P3 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB x ld p P r P0 P8 x add P r P1 P7 x sub p P6 p P r P3 P5 4/1/2008 CS152-Spring’08 CS252 S05

11 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p <R1> P8 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 P1 P2 P3 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB x ld p P r P0 P8 x add P r P1 P7 x sub p P6 p P r P3 P5 x add P P r P2 P1 4/1/2008 CS152-Spring’08 CS252 S05

12 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p <R1> P8 Free List P0 P1 P3 P2 P4 ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 P1 P2 P3 P4 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB x ld p P r P0 P8 x add P r P1 P7 x sub p P6 p P r P3 P5 x add P P r P2 P1 x ld P r P4 P3 4/1/2008 CS152-Spring’08 CS252 S05

13 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p <R1> P8 Free List P0 P1 P3 P2 P4 p <R1> ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 P1 P2 P8 P3 P4 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB Execute & Commit x ld p P r P0 x ld p P r P0 x P8 x add P r P1 P7 x sub p P6 p P r P3 P5 x add P P r P2 P1 x ld P r P4 P3 4/1/2008 CS152-Spring’08 CS252 S05

14 Physical Register Management
Rename Table <R6> P5 <R7> P6 <R3> P7 P0 Pn P1 P2 P3 P4 Physical Regs p P8 Free List P0 P1 P3 P2 P4 p <R1> p <R3> ld r1, 0(r3) add r3, r1, #4 sub r6, r7, r6 add r3, r3, r6 ld r6, 0(r1) P0 P1 P2 P8 P7 P3 P4 op p1 PR1 p2 PR2 ex use Rd PRd LPRd ROB x x ld p P r P0 P8 Execute & Commit x add P r P1 x add P r P1 x P7 x sub p P6 p P r P3 P5 x add P P r P2 P1 x ld P r P4 P3 4/1/2008 CS152-Spring’08 CS252 S05

15 CS152 Administrivia New shifted schedule - see website for details
Lab 4, PS 4, due Tuesday April 8 PRIZE (TBD) for winners in both unlimited and realistic categories of branch predictor contest Quiz 4, Thursday April 10 Quiz 5, Thursday April 24 Quiz 6, Thursday May 8 (last day of class) 4/1/2008 CS152-Spring’08 CS252 S05

16 Reorder Buffer Holds Active Instruction Window
… ld r1, (r3) add r3, r1, r2 sub r6, r7, r9 add r3, r3, r6 ld r6, (r1) add r6, r6, r3 st r6, (r1) (Older instructions) … ld r1, (r3) add r3, r1, r2 sub r6, r7, r9 add r3, r3, r6 ld r6, (r1) add r6, r6, r3 st r6, (r1) Commit Fetch Cycle t + 1 Execute (Newer instructions) Cycle t 4/1/2008 CS152-Spring’08 CS252 S05

17 Superscalar Register Renaming
During decode, instructions allocated new physical destination register Source operands renamed to physical register with newest value Execution unit only sees physical register numbers Inst 1 Inst 2 Op Src1 Src2 Dest Op Src1 Src2 Dest Update Mapping Rename Table Read Addresses Register Free List Write Ports Read Data Op PSrc1 PSrc2 PDest Op PSrc1 PSrc2 PDest Does this work? 4/1/2008 CS152-Spring’08 CS252 S05

18 Superscalar Register Renaming
Inst 1 Inst 2 Op Src1 Src2 Dest Op Src1 Src2 Dest Update Mapping Rename Table Read Addresses Register Free List Write Ports =? =? Read Data Must check for RAW hazards between instructions issuing in same cycle. Can be done in parallel with rename lookup. Doesn’t show that update reflects last dest. (jse) Op PSrc1 PSrc2 PDest Op PSrc1 PSrc2 PDest MIPS R10K renames 4 serially-RAW-dependent insts/cycle 4/1/2008 CS152-Spring’08 CS252 S05

19 When can we execute the load?
Memory Dependencies st r1, (r2) ld r3, (r4) When can we execute the load? 4/1/2008 CS152-Spring’08 CS252 S05

20 In-Order Memory Queue Execute all loads and stores in program order
=> Load and store cannot leave ROB for execution until all previous loads and stores have completed execution Can still execute loads and stores speculatively, and out-of-order with respect to other instructions 4/1/2008 CS152-Spring’08 CS252 S05

21 Conservative O-o-O Load Execution
st r1, (r2) ld r3, (r4) Split execution of store instruction into two phases: address calculation and data write Can execute load before store, if addresses known and r4 != r2 Each load address compared with addresses of all previous uncommitted stores (can use partial conservative check i.e., bottom 12 bits of address) Don’t execute load if any previous store address not known (MIPS R10K, 16 entry address queue) 4/1/2008 CS152-Spring’08 CS252 S05

22 Address Speculation st r1, (r2) ld r3, (r4) Guess that r4 != r2
Execute load before store address known Need to hold all completed but uncommitted load/store addresses in program order If subsequently find r4==r2, squash load and all following instructions => Large penalty for inaccurate address speculation 4/1/2008 CS152-Spring’08 CS252 S05

23 Memory Dependence Prediction (Alpha 21264)
st r1, (r2) ld r3, (r4) Guess that r4 != r2 and execute load before store If later find r4==r2, squash load and all following instructions, but mark load instruction as store-wait Subsequent executions of the same load instruction will wait for all previous stores to complete Periodically clear store-wait bits 4/1/2008 CS152-Spring’08 CS252 S05

24 Speculative Loads / Stores
Just like register updates, stores should not modify the memory until after the instruction is committed - A speculative store buffer is a structure introduced to hold speculative store data. 4/1/2008 CS152-Spring’08 CS252 S05

25 Speculative Store Buffer
Load Address L1 Data Cache Tag Data S V Tags Data Tag Data S V Tag Data S V Tag Data S V Tag Data S V Tag Data S V Store Commit Path Load Data On store execute: mark entry valid and speculative, and save data and tag of instruction. On store commit: clear speculative bit and eventually move data to cache On store abort: clear valid bit 4/1/2008 CS152-Spring’08 CS252 S05

26 Speculative Store Buffer
Load Address L1 Data Cache Tag Data S V Tags Data Tag Data S V Tag Data S V Tag Data S V Tag Data S V Tag Data S V Store Commit Path Load Data If data in both store buffer and cache, which should we use? Speculative store buffer If same address in store buffer twice, which should we use? Youngest store older than load 4/1/2008 CS152-Spring’08 CS252 S05

27 Datapath: Branch Prediction and Speculative Execution
Update predictors Branch Prediction Branch Resolution kill PC Fetch Decode & Rename Reorder Buffer Commit Reg. File Branch Unit ALU MEM Store Buffer D$ Execute 4/1/2008 CS152-Spring’08 CS252 S05

28 Acknowledgements These slides contain material developed and copyright by: Arvind (MIT) Krste Asanovic (MIT/UCB) Joel Emer (Intel/MIT) James Hoe (CMU) John Kubiatowicz (UCB) David Patterson (UCB) MIT material derived from course 6.823 UCB material derived from course CS252 4/1/2008 CS152-Spring’08 CS252 S05

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