1. HARDROC STATUS
6-Dec-18

2. HARDROC2 MODIFICATIONS
Minor bugs correction:
mask, memory pointer: dummy frame
Power pulsing:
Bandgap + ref Volages to be power pulsed
Dynamic range extension
Gain correction: 8 bits instead of 6
3 shapers and 3 thresholds:
10 fC, 100fC, 1pC (megas)
100fC, 1pC, 10pC (GRPC)
Bandgap redesigned
DAC : 3 DACs
The 3rd one different from the 2 others
Discri of the 3rd shaper: slightly different.
HARDROC2= HARDROC1 + modifs
=> HARDROC1= BACKUP
6-Dec-18
NSM, LAL/Omega

3. HARDROC2: FORSEEN MODIFICATIONS
6-Dec-18
NSM, LAL/Omega

4. HARDROC2: analog part Slow Channel PA Discri 0 FSB0 Discri 1 Gain FSB1
½,1/4,1/8,1/16 PA
Discri 0
FSB0
Discri 1
Gain FSB1
½,1/4,1/8,1/16
Discri 2
Gain FSB2
1/8,1/16,1/32,1/64
6-Dec-18
NSM, LAL/Omega

5. HARDROC2: Digital part (F.Dulucq)
Probe and Slow Control shift registers
- Multiplex these 2 registers (in, out, clock, reset)  save PADS (8  5)
- Select line added : default register is probe to prevent glitch on SC
- Extra PADS can be added for direct access to registers
6-Dec-18
NSM, LAL/Omega

6. HR2 Digital part: Default SC configuration (2)
Use Set / Reset of Flip-Flops for default configuration
Example default configuration : “011”
Can also be done with Q and Q* of Flip-Flops (already done for some bits
6-Dec-18
NSM, LAL/Omega

7. HR2 digital part: SC daisy chain (3)
Improve daisy chain between ASICs :
Add opposite edge FF at the end of shift registers
Allow to meet timing requirement between last FF of chip “N” and first FF of chip “N+1”
Inside chip  use clock reversing to prevent timing problem
6-Dec-18
NSM, LAL/Omega

8. HR2 digital part: Readout (4)
During readout, remove “bad frame” (address pointer error when chip is not full)
First irrelevant
frame
Capacity of 127 trigger instead of 128  change digital limitations (should be minor change in VHDL)
6-Dec-18
NSM, LAL/Omega

9. HR2 digital part: StartAcquisition (5)
Change for SPIROC like  “StartAcquisition” active on level.
RamFull  ChipSat (OK for SPIROC and HARDROC)
Allow to remove “RamFullExt” signal and to let DAQ stop acquisition
“StartAcquisition” should be now named “CtrlAcquisition”
6-Dec-18
NSM, LAL/Omega

10. HR2 digital part: StartReadOut and EndReadOut (6)
Add bypass for these 2 signals (SRO, ERO  SRO-B, ERO-B).
In red, StartReadOut and EndReadOut flow if chip “N” fails
Chip N can bypass itself by SC
Chip “N-1” and chip “N+1” can bypass chip “N” by SC
If Chip N fails :
Chip N-1 sends EndReadOut signal on EndReadOutBypass
Chip N+1 reads StartReadOut signal on StartReadOutBypass
6-Dec-18
NSM, LAL/Omega

11. HR2 digital part: Slow Control (7)
Add bypass jumpers on PCB
In red, SC flow if chip “N” fails
Default position is chip “N” reads chip “N-1”
If Chip N fails :
Switch N removed
Switch N+1  in position to read chip “N-1”
6-Dec-18
NSM, LAL/Omega

12. Data and TransmitOn: Redundancy
Each one is removable from bus line by SC
2 bus lines, OC drivers to drive 50 Ohms
Allow to remove one buffer that stick the bus line
6-Dec-18
NSM, LAL/Omega

13. PACKAGING in CQFP240: Yield problem
HARDROC1:
30 dies for µmegas PCB and 130 dies for 1m2 prototype
I2A company in California:
Price: ~3500$ for 100 or 1000 dies packaged in Plastic QFP240
~ 25€ / die (Q=100)
Pb of yield when packaging in QFP240: 40%
100 €/die
Administrative procedure quite complicated….
SYSTREL (Nantes):
Last offer (March 08) for bonding in Ceramic QFP240:
Package price
Small Q: 65 euros ht
Q= 100 dies: 47 euros ht /package,
Q= 250 dies: 38 euros ht /package
Bonding: 82 euros ht/ die
Between 120 and 150 euros/ die depending on the quantity
Delay: 4 to 8 weeks
HARDROC2: will be packaged in PQFP176
6-Dec-18
NSM, LAL/Omega

14. PACKAGE TQPP176
1.4 mm
6-Dec-18
NSM, LAL/Omega

15. ANNEX
6-Dec-18
NSM, LAL/Omega

16. Control signals and power supplies
HARDROC1 layout
Hadronic Rpc Detector Read Out Chip (AMS SiGe 0.35µm, Sept 06)
64 inputs, preamp + shaper+ 2 discris + memory + Full power pulsing
Compatible with 1st and 2nd generation DAQ : only 1 digital data output
Discris
4 mmx4 mm
Digital
memory 64
Analog
Channels
Dual DAC
Bandgap
Control signals and power supplies
6-Dec-18
NSM, LAL/Omega

17. HARDROC1: ANALOG. PART GAIN CORRECTION: RPC: 100 fC to 10pC
µMEGAS= 10fC up to 1pC
6-Dec-18
NSM, LAL/Omega

18. HARDROC1: Digital part
6-Dec-18
NSM, LAL/Omega

19. Multi Project Run vs Dedicated Run
HARDROC2: will be submitted in june 08 (MPW run)
MPW: 1k€/mm2 => Hardroc= 25 k€
25 dies delivered in September 08, to be packaged
About 300 dies available (no garanty): 100 euros/die + packaging
Price : 25 k€ € * nb_chips
Engineering run:
Wafer 8’’ Available area= mm2
1 reticle=20x20 mm2=400 mm2
=> 65 reticles/wafer
16 chips (25 mm2) / reticle => 1000 Hardroc/wafer
Cost : 150 k€ (masks) + 5k€/wafer
- Price : 150 k€ + 5 € * nb_chips
valuable for more than 1250 chips
6-Dec-18
NSM, LAL/Omega

20. Open collector signals after 1m long line
Rcollector=50Ω
Rcollector=500Ω
6-Dec-18
NSM, LAL/Omega

21. HV sparks (ESD) GRPC: HV=8 kV, PADs= a few pF
High spread resistor= isolates FE inputs
Micromegas: HV=400V, Pads= a few pF
Small spread resistor= NO ISOLATION of the FE inputs
1m2 => 100 Asic*64*a few pF~ 1nF
6-Dec-18
NSM, LAL/Omega

22. AC coupling necessary for detector > 10 cm2:
HV sparks (ESD)
ASIC inputs:
protection PADs (AMS library): robustness up to 2kV HBM (100pF)
AC coupling necessary for detector > 10 cm2:
Tests to be performed on HARDROC to determine the decoupling capacitance necessary to protect the FE against ESD
Maximum decoupling capacitor that can be integrated: ≈30pF (50µm x 600 µm ) and lost of signal => EXTERNAL CAP=500 pF/ch to ensure protection
Other drawbacks of a decoupling cap: Xtalk, space
6-Dec-18
NSM, LAL/Omega