1. EECS Components and Design Techniques for Digital Systems Lec 08 – Using, Modeling and Implementing FSMs
David Culler
Electrical Engineering and Computer Sciences
University of California, Berkeley
9/23/04
EECS150 F04 Culler Lec 8

2. Review: What’s an FSM? Often PLAs
Next state is function of state and input
Moore Machine: output is a function of the state
Mealy Machine: output is a function of state and input
inputA
State / output
inputB
inputA/outputA
State
inputB/outputB
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3. Review: Formal Design Process
Logic equations from table:
OUT = PS
NS = PS xor IN
Review of Design Steps:
1. Circuit functional specification
2. State Transition Diagram
3. Symbolic State Transition Table
4. Encoded State Transition Table
5. Derive Logic Equations
6. Circuit Diagram
FFs for state
CL for NS and OUT
Circuit Diagram:
XOR gate for ns calculation
DFF to hold present state
no logic needed for output ns ps
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EECS150 F04 Culler Lec 8

4. Review: Finite State Machine Representations
States: determined by possible values in sequential storage elements
Transitions: change of state
Clock: controls when state can change by controlling storage elements
Sequential Logic
Sequences through a series of states
Based on sequence of values on input signals
Clock period defines elements of sequence
In = 0
In = 1
100
010
110
111
001
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EECS150 F04 Culler Lec 8

5. Outline Review Typical uses of FSMs
Synchronous Seq. Circuits – safe composition
Timing
FSMs in verilog (reinforcing lab lecture)
State reduction and state assignment
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6. Recall: Parallel to Serial Converter
module ParToSer(LD, X, out, CLK);
input [3:0] X;
input LD, CLK;
output out;
reg out;
reg [3:0] Q;
assign out = Q[0];
(posedge CLK) begin
if (LD) Q <= X;
else Q <= {1’b0,Q[3:1]};
end
endmodule // ParToSer
One common use of FSMs is in adapters from one subsystem to another.
different data widths
different bit rates
different protocols, …
9/23/04
EECS150 F04 Culler Lec 8

7. Example: Byte-bit stream
Byte FIFO
init / LD
bit 0/pop
bit 1
pop
bit 2
controller
Shift register
bit 3 LD
bit 4
bit 5
Serial link
bit 6
bit 7 / LD
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8. Byte-bit stream with Rate Matching
Byte FIFO
init / LD
bit 0/pop
~rdy
bit 0’
bit 1
~rdy
rdy
rdy
~rdy
pop
bit 2
~rdy
rdy
controller
Shift register
bit 3
~rdy
rdy LD
bit 4
~rdy
rdy
bit 5
Serial link
~rdy
rdy
rdy
bit 6
~rdy
rdy
How would you implement this FSM?
bit 7 / LD
~rdy
rdy
9/23/04
EECS150 F04 Culler Lec 8

9. Another example: bus protocols
A bus is:
shared communication link
single set of wires used to connect multiple subsystems
A Bus is also a fundamental tool for composing large, complex systems (more later in the term)
systematic means of abstraction
Control
Datapath
Memory
Processor
Input
Output
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10. Example: Pentium System Organization
Processor/Memory
Bus
PCI Bus
I/O Busses
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11. Arbitration for the bus…
Device 1
Device N
Device 2
Grant
Req
Bus
Arbiter
Central arbitration shown here
Used in essentially all processor-memory busses and in high-speed I/O busses
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12. Simple Synchronous Protocol
I still want the bus
I want the bus
BReq
I’m done after this
You got it BG
nope
Mem grabs addr
CMD
Address
Rd+Addr
Proc grabs data
Data1
Data2
Data
Even memory busses are more complex than this
memory (slave) may take time to respond
it need to control data rate
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EECS150 F04 Culler Lec 8

13. Processor Side of Protocol - sketch
Idle
~BR
proc read
Request bus BR BG
Address
BR,RD, addr_enable
~BG
Data 1
BR, MDR_enable
Memory waits?
Additional outputs?
Memory side?
Data 2
~BR, MDR_enable
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EECS150 F04 Culler Lec 8

14. Simple Synchronous Protocol (cont)
I still want the bus
I want the bus
BReq
I’m done after this
You got it BG
nope
Mem grabs addr
CMD
Address
Rd+Addr
Proc grabs data
Data1
Data2
Data
w-addr
r-data1
idle
idle
req
req
r-data2
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EECS150 F04 Culler Lec 8

15. Fundamental Design Principle
Divide circuit into combinational logic and state
Localize feedback loops and make it easy to break cycles
Implementation of storage elements leads to various forms of sequential logic
Combinational Logic
Storage Elements
Outputs
State Outputs
State Inputs
Inputs
9/23/04
EECS150 F04 Culler Lec 8

16. Forms of Sequential Logic
Asynchronous sequential logic – “state” changes occur whenever state inputs change (elements may be simple wires or delay elements)
Synchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock)
Clock
9/23/04
EECS150 F04 Culler Lec 8

17. General Model of Synchronous Circuit
All wires, except clock, may be multiple bits wide.
Registers (reg)
collections of flip-flops
clock
distributed to all flip-flops
typical rate?
Combinational Logic Blocks (CL)
no internal state (no feedback)
output only a function of inputs
Particular inputs/outputs are optional
Optional Feedback
ALL CYCLES GO THROUGH A REG!
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18. Composing FSMs into larger designsCL CL
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19. Composing Moore FSMs Synchronous design methodology preserved Moore
state
output
next
state
output
next CL CL
Synchronous design methodology preserved
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20. Composing Mealy FSMs … Synchronous design methodology violated!!!
state
Output
Next
state
Output
Next CL CL
Synchronous design methodology violated!!!
Why do designers used them?
Few states, often more natural in isolation
Safe if latch all the outputs
Looks like a mealy machine, but isn’t really
What happens to the timing?
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21. State Time (Clock Period)
FSM timing
How long must this be?
State Time (Clock Period)
Clock
Inputs
What determines this?
Output logic propagation delay
State register propagation delay
Outputs
State (internal)
What determines min FSM cycle time (max clock rate)?
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22. Announcements Reading 8.4,7.4, 8.1
We touched on ideas from chapter 11, not in reader. Will be available on line.
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23. Finite State Machines in Verilog
Mealy outputs
next state
combinational
logic
Moore outputs
inputs
combinational
logic
current state
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24. Verilog FSM - Reduce 1s example
Change the first 1 to 0 in each string of 1’s
Example Moore machine implementation 1
zero [0]
one1 [0]
two1s
[1]
module Reduce(Out, Clock, Reset, In); output Out; input Clock, Reset, In;
reg Out; reg [1:0] CurrentState; // state register reg [1:0] NextState;
// State assignment
localparam STATE_Zero = 2’h0,
STATE_One1 = 2’h1,
STATE_Two1s = 2’h2,
STATE_X = 2’hX;
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EECS150 F04 Culler Lec 8

25. Moore Verilog FSM: combinational part
or CurrentState) begin
NextState = CurrentState;
Out = 1’b0;
case (CurrentState)
STATE_Zero: begin // last input was a zero if (In) NextState = STATE_One1; end
STATE_One1: begin // we've seen one 1 if (In) NextState = STATE_Two1s; else NextState = STATE_Zero; end
STATE_Two1s: begin // we've seen at least 2 ones Out = 1; if (~In) NextState = STATE_Zero; end
default: begin // in case we reach a bad state
Out = 1’bx;
NextState = STATE_X;
end
endcase
include all signals
that are input to state
and output equations 1
zero [0]
one1 [0]
two1s
[1]
Compute: output = G(state)
next state = F(state, in)
9/23/04
EECS150 F04 Culler Lec 8

26. Moore Verilog FSM: state part
// Implement the state register
(posedge Clock) begin if (Reset) CurrentState <= STATE_Zero; else CurrentState <= NextState;
end
endmodule 1
zero [0]
one1 [0]
two1s
[1]
Note: posedge Clock requires NONBLOCKING ASSIGNMENT.
Blocking Assignment <-> Combinational Logic
Nonblocking Assignment <-> Sequential Logic (Registers)
9/23/04
EECS150 F04 Culler Lec 8

27. Mealy Verilog FSM for Reduce-1s example
module Reduce(Clock, Reset, In, Out); input Clock, Reset, In; output Out; reg Out; reg CurrentState; // state register
reg NextState;
localparam STATE_Zero = 1’b0,
STATE_One = 1’b1;
Clock) begin
if (Reset) CurrentState <= STATE_Zero; else CurrentState <= NextState;
end (In or CurrentState) begin
NextState = CurrentState;
Out = 1’b0; case (CurrentState) zero: if (In) NextState = STATE_One;
one: begin // we've seen one if (In) NextState = STATE_One;
else NextState = STATE_Zero;
Out = In;
end
endcase
end endmodule
1/0
0/0
1/1
zero [0]
one1 [0]
Note: smaller state machine
Output = G(state, input)
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28. Restricted FSM Implementation Style
Mealy machine requires two always blocks
Register needs posedge Clock block
Input to output needs combinational block
Moore machine can be done with one always block, but….
E.g. simple counter
Very bad idea for general FSMs
This will cost you hours of confusion, don’t try it
We will not accept labs with this style for general FSMs
Use two always blocks!
Moore outputs
Share with state register, use suitable state encoding
9/23/04
EECS150 F04 Culler Lec 8

29. Single-always Moore Machine (Not Allowed!)
module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg [1:0] state; // state register parameter zero = 0, one1 = 1, two1s = 2; 1
zero [0]
one1 [0]
two1s
[1]
9/23/04
EECS150 F04 Culler Lec 8

30. Single-always Moore Machine (Not Allowed!)
clk) case (state) zero: begin out <= 0; if (in) state <= one1; else state <= zero; end one1: if (in) begin
state <= two1s;
out <= 1;
end else begin
state <= zero;
out <= 0;
end two1s: if (in) begin
end
default: begin
endcase endmodule
All outputs are registered
This is confusing: the
output does not change
until the next clock cycle
9/23/04
EECS150 F04 Culler Lec 8

31. Finite State Machines Recommended FSM implementation style
Implement combinational logic using one always block
Implement an explicit state register using a second always block
Mealy outputs
next state
combinational
logic
Moore outputs
inputs
combinational
logic
current state
9/23/04
EECS150 F04 Culler Lec 8

32. FSM Optimization State Reduction: Example: Odd parity checker.
Motivation:
lower cost
fewer flip-flops in one-hot implementations
possibly fewer flip-flops in encoded implementations
more don’t cares in NS logic
fewer gates in NS logic
Simpler to design with extra states then reduce later.
Example: Odd parity checker.
Two machines - identical behavior.
9/23/04
EECS150 F04 Culler Lec 8

33. State Reduction State Reduction is based on:
Two states are equivalent if, for each member of the set of inputs, they give exactly the same output and send the circuit either to the same state or to an equivalent state.
If two states are equivalent, one can be eliminated without effecting the behavior of the FSM.
Several algorithms exist:
Row matching method.
Implication table method.
“Row Matching” is based on the state-transition table:
If two states have the same output, and both transition to the same next state, or both transition to each other, or both self-loop, then they are equivalent.
Combine the equivalent states into a new renamed state.
Repeat until no more states are combined.
Note: This algorithm is slightly different than the book.
9/23/04
EECS150 F04 Culler Lec 8

34. Row Matching Example State Transition Table NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e f
e a f
f g f
g a f
9/23/04
EECS150 F04 Culler Lec 8

35. Row Matching Example (cont)
NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e f
e a f
f e f
Reduced State Transition Diagram
NS output
PS x=0 x=1 x=0 x=1
a a b
b c d
c a d
d e d
e a d
9/23/04
EECS150 F04 Culler Lec 8

36. State Reduction
The “row matching” method is not guaranteed to result in the optimal solution in all cases, because it only looks at pairs of states.
For example:
Another (more complicated) method guarantees the optimal solution:
“Implication table” method:
cf. Mano, chapter 9
What ‘rule of thumb” heuristics?
9/23/04
EECS150 F04 Culler Lec 8

37. State Maps “K-maps” are used to help visualize good encodings.
Assignment
State q2 q1 q0 S S S S S
Assignment
State q2 q1 q0 S S S S S
“K-maps” are used to help visualize good encodings.
Adjacent states in the STD should be made adjacent in the map.
9/23/04
EECS150 F04 Culler Lec 8

38. State Assignment
Alternative heuristics based on input and output behavior as well
as transitions:
Adjacent assignments to:
states that share a common next state
(group 1's in next state map)
states that share a common ancestor state
(group 1's in next state map)
states that have common output behavior
(group 1's in output map)
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EECS150 F04 Culler Lec 8

39. Summary FSMs are critical tool in your design toolbox
Adapters, Protocols, Datapath Controllers, …
They often interact with other FSMs
Important to design each well and to make them work together well.
Keep your verilog FSMs clean
Separate combinational part from state update
Good state machine design is an iterative process
State encoding
Reduction
Assignment
9/23/04
EECS150 F04 Culler Lec 8