1. ICIEV 2014 Dhaka, Bangladesh
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
May 23 – 24, 2014

2. Wichita State University (WSU), USA
ICIEV 2014
Dhaka, Bangladesh
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Dr. Abu Asaduzzaman
Computer Architecture & Parallel Programming Laboratory (CAPPLab)
Department of Electrical Engineering and Computer Science (EECS)
College of Engineering
Wichita State University (WSU), USA
May 23 – 24, 2014

3. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Outline ►
Introduction
Problem Statement and Contributions
Background Work and Motivation
Proposed Smart Victim Cache for Multicore Systems
Smart Victim Cache Design
Smart Victim Cache Work-Flow
Simulation Details
Workloads
Inputs and Outputs
Results and Discussion
Conclusions
QUESTIONS?
Any time!

4. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Authors
Abu Asaduzzaman, Assistant Professor
EECS Department, Wichita State University (WSU), USA
Director, Computer Arch & Parallel Prog Lab (CAPPLab)
Mark P. Allen, MS/CS Student
Expected Graduation: Fall 2014
Tania Jareen, MS/EE Student
Graduation: Spring 2014

5. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Introduction
Problem Statement
Studies show that cache locking may improve performance.
However, aggressive cache locking may reduce the effective cache size and may introduce additional configuration difficulties, especially for multicore architectures.
Furthermore, there may be other restrictions (example: PowerPC 750GX processor does not allow cache locking at level-1).
Single-Core System
Multicore System

6. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Introduction
Contributions
In this work, we propose a Smart Victim Cache (SVC)-assisted caching technique that eliminates traditional cache locking without compromising the performance to power ratio.
In addition to functioning as a normal victim cache, the proposed SVC holds memory blocks that may cause higher cache misses and supports stream buffering to increase cache hits.
Multicore System with
Smart Victim Cache

7. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Introduction
Background Work
Multicore architecture has advantage to improve the performance to power ratio.
Cache management and data consistency are more difficult in multicore architecture.
Multicore caches make the average memory latency large and unpredictable due to cache’s dynamic behavior.
Multicore caches require high power supply to keep them functional.
Selective preloading, victim buffer, stream buffering, victim cache, and cache locking.
Multicore System with
Smart Victim Cache

8. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Introduction
Motivation
Cache locking in multicore architecture is very difficult and may not be beneficial.
Some processors (like PowerPC 750GX) do not allow cache locking at CL1.
Therefore, we propose a smart victim cache that provides multiple important services including storing block address and Cache Miss Information (BACMI) entries and Stream Buffering Blocks (SBB) in addition to the regular Victim Cache Blocks (VCB) to improve the performance to power ratio.
Multicore System with
Smart Victim Cache

9. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Outline ►
Introduction
Problem Statement and Contributions
Background Work and Motivation
Proposed Smart Victim Cache for Multicore Systems
Smart Victim Cache Design
Smart Victim Cache Work-Flow
Simulation Details
Workloads
Inputs and Outputs
Results and Discussion
Conclusions

10. Proposed SVC for Multicore Systems
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Proposed SVC for Multicore Systems
SVC Design
Victim Cache Blocks (VCB)
Stream Buffering Blocks (SBB)
Cache Miss Information (BACMI)
Multicore System with Smart Victim Cache
BACMI entries for different SVC sizes

11. Proposed SVC for Multicore Systems
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Proposed SVC for Multicore Systems
SVC Work-Flow
SVC if CL1 miss
SWAP if SVC hit
Stream Buffering if CL2 miss
Requested Blk goes to CL2, CL1
If CL1 full, VB goes to SVC
Other Blks go to SBB

12. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Simulation Details
Workloads
The workload defines all possible scenarios and environmental conditions that the system-under-study will be operating under.
Applications used: Moving Picture Experts Group’s MPEG-4 (part-2) decoding, Advanced Video Coding (H.264/AVC) decoding, Fast Fourier Transform (FFT), and Matrix Inversion (MI).

13. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Simulation Details
Inputs
Number of cores: 4
SVC size: 2, 4, 8, 16, and 32 KB
CL1 (I1/D1) size: 32 (16/16) KB
CL2 (256, 512, 1024, 2048, 4096 KB
Line size: 128 Byte
Degree of associativity level: 8-way
Outputs
Average latency per task
Total power consumption

14. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Outline ►
Introduction
Problem Statement and Contributions
Background Work and Motivation
Proposed Smart Victim Cache for Multicore Systems
Smart Victim Cache Design
Smart Victim Cache Work-Flow
Simulation Details
Workloads
Inputs and Outputs
Results and Discussion
Conclusions

15. Results and Discussion
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Results and Discussion
Impact of SVC Size
For MPEG-4, SVC shows improvement over CL2 cache locking.
Total power consumption decreases as SVC’s size increases.

16. Results and Discussion
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Results and Discussion
Impact of SVC and CL2 Size
No positive impact on average latency per task for MPEG-4 & FFT.
Total power consumption increases as CL2 size increases.

17. Results and Discussion
“An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Results and Discussion
Comparison between SVC and Cache Locking
Latency Vs. Cache Locking
Power Vs. Cache Locking
25% locking is optimal
For both latency and power,
SVC is better than cache locking

18. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Conclusions
In this work, we introduce a Smart Victim Cache (SVC)-assisted caching technique. The proposed SVC functions as an improved victim cache (stores memory blocks that may cause higher cache misses), helps eliminating cache locking by holding BACMI Entries, and supports stream buffering.
According to the simulated results, the proposed SVC helps decrease the total power consumption up to 21% and the average memory latency up to 17% when compared with a CL2 cache locking mechanism without SVC.

19. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
Conclusions
Considering the performance to power ratio improvement, the proposed SVC-assisted cache memory subsystem it is a better choice (than cache locking implementation) for power-aware multicore computing systems.
We plan to explore the impact of SVC on performance and power consumption for low-power high performance computing (HPC) systems in our next endeavor.

20. “An Effective Locking-Free Caching Technique for Power-Aware Multicore Computing Systems”
QUESTIONS?
Contact: Abu Asaduzzaman Phone:
Thank You!