1. ECE 448
Lecture 6
Modeling of Circuits with a Regular Structure Aliases, Constants, Packages Mixing Design Styles
ECE 448 – FPGA and ASIC Design with VHDL

2. Reading Required Recommended P. Chu, FPGA Prototyping by VHDL Examples
Chapter 3.6, Constants and Generics
Recommended
S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design
Chapter 6.6.4, Generate Statements
Chapter A.7.5, Generate Statement
Chapter A.10.9, Using Subcircuits with Generic
Parameters
Chapter A.11, Common Errors in VHDL Code
ECE 448 – FPGA and ASIC Design with VHDL

3. Generate scheme for equations
ECE 448 – FPGA and ASIC Design with VHDL

4. Concurrent statements
Data-flow VHDL
Major instructions
Concurrent statements
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)
ECE 448 – FPGA and ASIC Design with VHDL

5. PARITY Example
ECE 448 – FPGA and ASIC Design with VHDL

6. PARITY: Block Diagram
ECE 448 – FPGA and ASIC Design with VHDL

7. PARITY: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY parity IS
PORT(
parity_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
parity_out : OUT STD_LOGIC );
END parity;
ECE 448 – FPGA and ASIC Design with VHDL

8. PARITY: Block Diagram xor_out(1) xor_out(2) xor_out(3) xor_out(4)
ECE 448 – FPGA and ASIC Design with VHDL

9. PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: std_logic_vector (6 downto 1);
BEGIN
xor_out(1) <= parity_in(0) XOR parity_in(1);
xor_out(2) <= xor_out(1) XOR parity_in(2);
xor_out(3) <= xor_out(2) XOR parity_in(3);
xor_out(4) <= xor_out(3) XOR parity_in(4);
xor_out(5) <= xor_out(4) XOR parity_in(5);
xor_out(6) <= xor_out(5) XOR parity_in(6);
parity_out <= xor_out(6) XOR parity_in(7);
END parity_dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

10. PARITY: Block Diagram (2)
xor_out(0)
xor_out(1)
xor_out(2)
xor_out(3)
xor_out(4)
xor_out(5)
xor_out(6)
xor_out(7)
ECE 448 – FPGA and ASIC Design with VHDL

11. PARITY: Architecture ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 downto 0);
BEGIN
xor_out(0) <= parity_in(0);
xor_out(1) <= xor_out(0) XOR parity_in(1);
xor_out(2) <= xor_out(1) XOR parity_in(2);
xor_out(3) <= xor_out(2) XOR parity_in(3);
xor_out(4) <= xor_out(3) XOR parity_in(4);
xor_out(5) <= xor_out(4) XOR parity_in(5);
xor_out(6) <= xor_out(5) XOR parity_in(6);
xor_out(7) <= xor_out(6) XOR parity_in(7);
parity_out <= xor_out(7);
END parity_dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

12. PARITY: Architecture (2)
ARCHITECTURE parity_dataflow OF parity IS
SIGNAL xor_out: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
xor_out(0) <= parity_in(0);
G2: FOR i IN 1 TO 7 GENERATE
xor_out(i) <= xor_out(i-1) XOR parity_in(i);
END GENERATE G2;
parity_out <= xor_out(7);
END parity_dataflow;
ECE 448 – FPGA and ASIC Design with VHDL

13. For Generate Statement
label: FOR identifier IN range GENERATE
BEGIN
{Concurrent Statements}
END GENERATE;
ECE 448 – FPGA and ASIC Design with VHDL

14. Generate scheme for components
ECE 448 – FPGA and ASIC Design with VHDL

15. component instantiation (port map)
Structural VHDL
Major instructions
component instantiation (port map)
component instantiation with generic
(generic map, port map)
generate scheme for component instantiations
(for-generate)
ECE 448 – FPGA and ASIC Design with VHDL

16. Example 1
ECE 448 – FPGA and ASIC Design with VHDL

17. Example 1 s f w ECE 448 – FPGA and ASIC Design with VHDL 1 3 4 2 7 811 s 1 3 4 7 12 15 2 f
ECE 448 – FPGA and ASIC Design with VHDL

18. A 4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux4to1 ;
ARCHITECTURE Dataflow OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END Dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

19. Straightforward code for Example 1
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Example1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END Example1 ;
ECE 448 – FPGA and ASIC Design with VHDL

20. Straightforward code for Example 1
ARCHITECTURE Structure OF Example1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ;
Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;
Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;
Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
ECE 448 – FPGA and ASIC Design with VHDL

21. Modified code for Example 1
ARCHITECTURE Structure OF Example1 IS
COMPONENT mux4to1
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;
END GENERATE ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
ECE 448 – FPGA and ASIC Design with VHDL

22. Example 2
ECE 448 – FPGA and ASIC Design with VHDL

23. Example 2 w w y y w w y y y y En y y w y y w y y y y w w y En y y w w1 1 3 15 w w y y 2 14 y y 1 13 En y y 12 w y y 1 3 11 w y y 2 10 y y 1 9 w 3 w y 1 3 En y y 8 w w y 2 2 y 1 En y w En w y y 1 3 7 w y y 2 6 y y 1 5 En y y 4 w y y 1 3 3 w y y 2 2 y y 1 1 En y y
ECE 448 – FPGA and ASIC Design with VHDL

24. A 2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE Dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= "0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111",
"0000" WHEN OTHERS ;
END Dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

25. VHDL code for Example 2 (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec4to16 IS
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END dec4to16 ;
ECE 448 – FPGA and ASIC Design with VHDL

26. VHDL code for Example 2 (2)
ARCHITECTURE Structure OF dec4to16 IS
COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i+3 DOWNTO 4*i) );
END GENERATE ;
Dec_left: dec2to4 PORT MAP ( w(3 DOWNTO 2), En, m ) ;
END Structure ;
ECE 448 – FPGA and ASIC Design with VHDL

27. Example 3 Variable Rotator
ECE 448 – FPGA and ASIC Design with VHDL

28. Example 3: Variable rotator - Interface16 4 B
A <<< B 16 C
ECE 448 – FPGA and ASIC Design with VHDL

29. Block diagram
ECE 448 – FPGA and ASIC Design with VHDL

30. VHDL code for a 16-bit 2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1_16 IS
PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s : IN STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END mux2to1_16 ;
ARCHITECTURE dataflow OF mux2to1_16 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

31. Fixed rotation <<< 3 <<< 5
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13)
<<< 3
y <= a(12 downto 0) & a(15 downto 13);
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0) a(15) a(14) a(13) a(12) a(11)
<<< 5
y <= a(10 downto 0) & a(15 downto 11);
ECE 448 – FPGA and ASIC Design with VHDL

32. Fixed rotation by L positions
a(15) a(14) a(13) a(12) a(11) a(10) a(9) a(8) a(7) a(6) a(5) a(4) a(3) a(2) a(1) a(0)
a(15-L) a(15-L-1) a(1) a(0) a(15) a(14) a(15-L+2) a(15-L+1)
<<< L
y <= a(15-L downto 0) & a(15 downto 15-L+1);
ECE 448 – FPGA and ASIC Design with VHDL

33. VHDL code for for a fixed 16-bit rotator
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fixed_rotator_left_16 IS
GENERIC ( L : INTEGER := 1);
PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END fixed_rotator_left_16 ;
ARCHITECTURE dataflow OF fixed_rotator_left_16 IS
BEGIN
y <= a(15-L downto 0) & a(15 downto 15-L+1);
END dataflow ;
ECE 448 – FPGA and ASIC Design with VHDL

34. Structural VHDL code for for a variable 16-bit rotator (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY variable_rotator_16 is
PORT(
A : IN STD_LOGIC_VECTOR(15 downto 0);
B : IN STD_LOGIC_VECTOR(3 downto 0);
C : OUT STD_LOGIC_VECTOR(15 downto 0) );
END variable_rotator_16;
ECE 448 – FPGA and ASIC Design with VHDL

35. Structural VHDL code for for a variable 16-bit rotator (2)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ARCHITECTURE structural OF variable_rotator_16 IS
COMPONENT mux2to1_16
PORT ( w0 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
w1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s : IN STD_LOGIC ;
f : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END COMPONENT ;
COMPONENT fixed_rotator_left_16
GENERIC ( L : INTEGER := 1);
PORT ( a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
ECE 448 – FPGA and ASIC Design with VHDL

36. Structural VHDL code for for a variable 16-bit rotator (3)
TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0);
SIGNAL Al : array1;
SIGNAL Ar : array2;
BEGIN
Al(0) <= A;
G: FOR i IN 0 TO 3 GENERATE
ROT_I: fixed_rotator_left_16
GENERIC MAP (L => 2** i)
PORT MAP ( a => Al(i) ,
y => Ar(i));
MUX_I: mux2to1_16 PORT MAP (w0 => Al(i),
w1 => Ar(i),
s => B(i),
f => Al(i+1));
END GENERATE;
C <= Al(4);
END variable_rotator_16;
ECE 448 – FPGA and ASIC Design with VHDL

37. Block diagram
ECE 448 – FPGA and ASIC Design with VHDL

38. Aliases
ECE 448 – FPGA and ASIC Design with VHDL

39. Aliases Example: Syntax: ALIAS name : type := expression;
signal IR : std_logic_vector(31 downto 0);
alias IR_opcode : std_logic_vector(5 downto 0) is IR(31 downto 26);
alias IR_reg1_addr : std_logic_vector(4 downto 0) is IR(25 downto 21);
alias IR_reg2_addr : std_logic_vector(4 downto 0) is IR(20 downto 16);
ECE 448 – FPGA and ASIC Design with VHDL

40. Constants
ECE 448 – FPGA and ASIC Design with VHDL

41. Constants Examples: Syntax: CONSTANT name : type := value;
CONSTANT init_value : STD_LOGIC_VECTOR(3 downto 0) := "0100";
CONSTANT ANDA_EXT : STD_LOGIC_VECTOR(7 downto 0) := X"B4";
CONSTANT counter_width : INTEGER := 16;
CONSTANT buffer_address : INTEGER := 16#FFFE#;
CONSTANT clk_period : TIME := 20 ns;
CONSTANT strobe_period : TIME := ms;
ECE 448 – FPGA and ASIC Design with VHDL

42. Constants - features Constants can be declared in a
PACKAGE, ENTITY, ARCHITECTURE
When declared in a PACKAGE, the constant
is truly global, for the package can be used
in several entities.
When declared in an ARCHITECTURE, the
constant is local, i.e., it is visible only within this architecture.
When declared in an ENTITY declaration, the constant
can be used in all architectures associated with this entity.
ECE 448 – FPGA and ASIC Design with VHDL

43. Packages
ECE 448 – FPGA and ASIC Design with VHDL

44. Explicit Component Declaration versus Package
Explicit component declaration is when you declare components in main code
When have only a few component declarations, this is fine
When have many component declarations, use packages for readability
Packages also help with portability and sharing of libraries among many users in a company
Remember, the actual instantiations always take place in main code
Only the declarations can be in main code or package
ECE 448 – FPGA and ASIC Design with VHDL

45. Explicit Component Declaration Tips
For simple projects put entity .vhd files all in same directory
Declare components in main code
If using Aldec, make sure compiler knows the correct hierarchy
From lowest to highest
Xilinx will figure out hierarchy automatically
ECE 448 – FPGA and ASIC Design with VHDL

46. METHOD #2: Package component declaration
Components declared in package
Actual instantiations and port maps always in main code
ECE 448 – FPGA and ASIC Design with VHDL

47. Packages
Instead of declaring all components can declare all components in a PACKAGE, and INCLUDE the package once
This makes the top-level entity code cleaner
It also allows that complete package to be used by another designer
A package can contain
Components
Functions, Procedures
Types, Constants
ECE 448 – FPGA and ASIC Design with VHDL

48. Package – example (1) LIBRARY ieee ; USE ieee.std_logic_1164.all ;
PACKAGE GatesPkg IS
COMPONENT mux2to1
PORT (w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
COMPONENT priority
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
ECE 448 – FPGA and ASIC Design with VHDL

49. Package – example (2) COMPONENT dec2to4
PORT (w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END COMPONENT ;
COMPONENT regn
GENERIC ( N : INTEGER := 8 ) ;
PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Enable, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
ECE 448 – FPGA and ASIC Design with VHDL

50. Package – example (3)
constant ADDAB : std_logic_vector(3 downto 0) := "0000";
constant ADDAM : std_logic_vector(3 downto 0) := "0001";
constant SUBAB : std_logic_vector(3 downto 0) := "0010";
constant SUBAM : std_logic_vector(3 downto 0) := "0011";
constant NOTA : std_logic_vector(3 downto 0) := "0100";
constant NOTB : std_logic_vector(3 downto 0) := "0101";
constant NOTM : std_logic_vector(3 downto 0) := "0110";
constant ANDAB : std_logic_vector(3 downto 0) := "0111";
END GatesPkg;
ECE 448 – FPGA and ASIC Design with VHDL

51. Package usage (1) ECE 448 – FPGA and ASIC Design with VHDL
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.GatesPkg.all;
ENTITY priority_resolver1 IS
PORT (r : IN STD_LOGIC_VECTOR(5 DOWNTO 0) ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
clk : IN STD_LOGIC;
en : IN STD_LOGIC;
t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END priority_resolver1;
ARCHITECTURE structural OF priority_resolver1 IS
SIGNAL p : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL q : STD_LOGIC_VECTOR (1 DOWNTO 0) ;
SIGNAL z : STD_LOGIC_VECTOR (3 DOWNTO 0) ;
SIGNAL ena : STD_LOGIC ;
ECE 448 – FPGA and ASIC Design with VHDL

52. Package usage (2) ECE 448 – FPGA and ASIC Design with VHDL BEGIN
u1: mux2to1 PORT MAP ( w0 => r(0) ,
w1 => r(1),
s => s(0),
f => p(0));
p(1) <= r(2);
p(2) <= r(3);
u2: mux2to1 PORT MAP ( w0 => r(4) ,
w1 => r(5),
s => s(1),
f => p(3));
u3: priority PORT MAP ( w => p,
y => q,
z => ena);
u4: dec2to4 PORT MAP ( w => q,
En => ena,
y => z);
u5: regn GENERIC MAP ( N => 4)
PORT MAP ( D => z ,
Enable => En ,
Clock => Clk,
Q => t );
END structural;
ECE 448 – FPGA and ASIC Design with VHDL

53. Aldec Compilation Order
Include package before top-level
ECE 448 – FPGA and ASIC Design with VHDL

54. Inside of an Architecture
Mixing Design Styles
Inside of an Architecture
ECE 448 – FPGA and ASIC Design with VHDL

55. VHDL Design Styles synthesizable VHDL Design Styles dataflow
structural
behavioral
Concurrent
statements
Components and
interconnects
Sequential statements
Registers
Shift registers
Counters
State machines
synthesizable
ECE 448 – FPGA and ASIC Design with VHDL

56. Mixed Style Modeling architecture ARCHITECTURE_NAME of ENTITY_NAME is
Here you can declare signals, constants, types, etc.
Component declarations
begin
Concurrent statements:
Concurrent simple signal assignment
Conditional signal assignment
Selected signal assignment
Generate statement
Component instantiation statement
Process statement
inside process you can use only sequential statements
end ARCHITECTURE_NAME;
Concurrent Statements
ECE 448 – FPGA and ASIC Design with VHDL

57. PRNG Example (1) library IEEE; use IEEE.STD_LOGIC_1164.all;
use work.prng_pkg.all;
ENTITY PRNG IS
PORT( Coeff : in std_logic_vector(4 downto 0);
Load_Coeff : in std_logic;
Seed : in std_logic_vector(4 downto 0);
Init_Run : in std_logic;
Clk : in std_logic;
Current_State : out std_logic_vector(4 downto 0));
END PRNG;
ARCHITECTURE mixed OF PRNG is
signal Ands : std_logic_vector(4 downto 0);
signal Sin : std_logic;
signal Coeff_Q : std_logic_vector(4 downto 0);
signal Shift5_Q : std_logic_vector(4 downto 0);
ECE 448 – FPGA and ASIC Design with VHDL

58. PRNG Example (2) END mixed; -- Data Flow G: FOR I IN 0 TO 4 GENERATE
Ands(I) <= Coeff_Q(I) AND Shift5_Q(I);
END GENERATE;
Sin <= Ands(0) XOR Ands(1) XOR Ands(2) XOR Ands(3) XOR Ands(4);
Current_State <= Shift5_Q;
-- Behavioral
Coeff_Reg: PROCESS(Clk)
BEGIN
IF Clk'EVENT and Clk = '1' THEN
IF Load_Coeff = '1' THEN
Coeff_Q <= Coeff;
END IF;
END PROCESS;
-- Structural
Shift5_Reg : Shift5 PORT MAP ( D => Seed,
Load => Init_Run,
Sin => Sin,
Clock => Clk,
Q => Shift5_Q);
END mixed;
ECE 448 – FPGA and ASIC Design with VHDL