1. Analog-to-Digital Converters
Lecture L11.2
(Verilog)
Section 11.3

2. Analog-to-Digital Converters
Converts analog signals to digital signals
8-bit: 0 – 255
10-bit: 0 – 1023
12-bit: 0 – 4095
Successive Approximation

3. Method of Successive Approximation

4. Implementing Successive Approximation

5. ADC0831 8-Bit Serial I/O A/D Converter

9. ADC0831 Timing

10. Voltmeter Logic
Block Diagram

12. module binbcd9(B,P);
input [8:0] B;
output [10:0] P;
reg [10:0] P;
reg [19:0] z;
integer i;
begin
for(i = 0; i <= 19; i = i+1)
z[i] = 0;
z[11:3] = B;
for(i = 0; i <= 5; i = i+1)
if(z[12:9] > 4)
z[12:9] = z[12:9] + 3;
if(z[16:13] > 4)
z[16:13] = z[16:13] + 3;
z[19:1] = z[18:0];
end
P = z[19:9];
endmodule

14. Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Q6 & Q7 (CS) Data Out (DO) !Q3 shift (S)
!Q3 shift (S)
[Q7..Q4] == 10
(Capture)
!Q3 display (D)

15. Q1 Q0
1.0 MHz Q2
0.5 MHz Q3
0.25 MHz
2.0 MHz
Clock
4.0 MHz

16. Q3
CLK Q7 Q6 CS DO
Xilinx XC95108
PC84 CPLD
Clock Divider
Counter Q7..Q0
4 MHz Clock
ADC0831
Interface

17. Q3 Q4 Q5 Q6 Q7 Q3 (CLK) Q6 & Q7 (CS) Data Out (DO) !Q3 shift (S)
!Q3 display (D)
[Q7..Q4] == 10
(Capture)
Q6 & Q7 (CS) Q3 Q4 Q5 Q6 Q7
Q3 (CLK)
Data Out (DO)
!Q3 shift (S)

18. Count Detect Logic
(Q7..Q4 = 10102)
Capture
Xilinx XC95108
PC84 CPLD
Clock Divider
Counter Q7..Q0
4 MHz Clock Q3 Q7 Q6
CLK CS DO
ADC0831
Interface
Display Register
D7..D0
Clock
Load
Shift Register
S7..S0
Data
!Q3

19. Simulation of adconv

20. Binary-to-BCD Converter 7-Segment Decoder 7 Voltage Display a..g
Binary-to-BCD
Converter
Hundreds Tens Units
7-Segment
Decoder 7
Voltage
Display
a..g
Xilinx XC95108
PC84 CPLD
Display Register
D7..D0
Clock
Load
(Shift Register S7..S0)
(Capture)
(!Q3)
dpt 1