1. STATIC NOISE ANALYSIS METHODS AND ALGORITHMS
Final Presentation
201C : Modeling of VLSI Circuits
Amarnath Kasibhatla
Electrical Engineering, UCLA
06/12/2009

2. OUTLINE Introduction Motivation for Static Noise Analysis (SNA)
Noise Margin criteria
Harmony: SNA seed paper
Aggressor alignment for worst case noise
SNA using Timing Windows
Non-linear superposition of noise sources
Conclusions
References

3. INTRODUCTION
Static noise analysis is the study of impact of various sources of noise onto a stable net holding a valid digital value.
Noise in Digital circuits is critical because it can cause functional failure.
Noise has become a metric in the design of a digital system in deep sub-micron era.
Even more critical for memory circuits.
Noise margin is defined in a generic way as the amount of deviation from logic HIGH and logic LOW values that a digital gate of can tolerate at its input without corrupting the output

4. MOTIVATION
Noise coupled onto static nodes can corrupt the logic value stored in a latch.
Noise coupled onto Dynamic node can propagate to the next stage and cause functional failure.
Noise induced onto the signal of victim can increase the delay and cause timing failure and hence functional failure.

5. NOISE MECHANISMS
Coupling noise due to capacitive coupling of victim net to the aggressor net. The peak value of the Vvictim depends on the C1 and C2. The pulse width roughly depends on RL*(C1+C2).

6. NOISE MECHANISMS - CONTD
Propagated noise : Noise at the inputs of gates will appear at the outputs as glitches in complementary and dynamic logic gates.
Severity of glitch depends on how strongly the gates are skewed.

7. Noise Mechanisms - Contd
Charge Sharing can happen through input switching or through sub-threshold leakage of the NMOS stack devices in dynamic logic.
Somewhat alleviated with the aid of feedback keeper devices.
Capacitive feedback can result in noise being coupled onto input from intermediate node or from input to directly onto the output nodes
Not a serious issue in many cases, especially for complex circuits

8. Introduction
Motivation for Static Noise Analysis (SNA)
Noise Margin criteria
Harmony: SNA seed paper
Aggressor alignment for worst case noise
SNA using Timing Windows
Non-linear superposition of noise sources
Conclusions
References

9. NOISE MARGIN CRITERIA
Essential stability requirement is the condition when the latch state doesn’t change in the presence of noise
Let and be the voltages on nodes A and B, be respectively f and g. f and g are the transfer functions of gates I and II, which means y = f(x) and x = g(y).
The latch will be stable in the presence of the series-voltage dc noise sources ( and ) on evaluation nodes and , if :
However this criteria is very conservative and pessimistic.

10. NOISE MARGIN CRITERIA – Contd.
More generic criteria: Every restoring logic gate, when acted upon by a noise stimulus, must have a time-domain dc-noise sensitivity that is always less than one.
The noise stimulus acts to bias the gate, while the dc-noise sensitivity examines the subsequent amplification of additional fluctuations of the lowest possible frequency content.
The main source of conservatism in the noise-stability metric comes in applying this test at every restoring logic gate rather than only at latches.

11. Introduction
Motivation for Static Noise Analysis (SNA)
Noise Margin criteria
Harmony: SNA seed paper
Aggressor alignment for worst case noise
SNA using Timing Windows
Non-linear superposition of noise sources
Conclusions
References

12. HARMONY – SNA METHOD KEY IDEAS:
Two-level hierarchical implementation for Macro and Global level noise analysis.
In each Macro it constructs graphs for all the digital circuits for which noise analysis is done.
Sensitizations are different input conditions under which noise from a source node will propagate to a target node.
Sensitizations are determined through Boolean satisfiability of constraint relations determined by functional extractions.
Once paths are established from all noise sources, the total noise at the output is found from superposition principle.

13. HARMONY – Noise Graphs
Edges are dawn between nodes where noise propagation is possible and which are biased at dc bias points with small signal gains greater than unity

14. Noise Analysis method
Noise analysis starts with calculating, through transistor level simulations, the noise appearing at each output along a path in the noise graph.
Having established DC voltage levels, different input combinations that will upset the voltage at each node along the path are observed through sensitizations.
To sensitize for noise at O due to capacitive coupling on node D, logic constraint relations are established depending on type of noise propagating from D to O (propagation noise):

15. Noise Analysis method - Example
Using the sensitizations table to calculate noise propagated onto the node O under different conditions to find out the worst case noise.
Similarly sensitization table for other noise sources like charge sharing, capacitive feedback and capacitive coupling are built.
The worst case noise at O is calculated using superposition.

16. HARMONY – TWO LEVEL HIERARCHY

17. HARMONY – Macro level
The worst case noise is propagated for all paths while simultaneously checking for stability criteria.
Hazard free logic constraints are used to avoid certain sensitizations which cannot happen (similar to false paths in Static timing analysis).
Timing of different noise sources is taken into consideration before applying superposition.
Port models of Macros are prepared for global level noise analysis.

18. HARMONY – Global Level
Global level HARMONY deals with interconnects connecting different macros. The interfaces to macros are using the port models for macros.

19. HARMONY – Global level
The worst case noise is calculated using above mixed integer programming problem. Let Ci be the noise injected on the victim by ith aggressor. Xi is the binary variable indicating whether aggressor is switching.

20. Introduction
Motivation for Static Noise Analysis (SNA)
Noise Margin criteria
Harmony: SNA seed paper
Aggressor alignment for worst case noise
SNA using Timing Windows
Non-linear superposition of noise sources
Conclusions
References

21. AGGRESSOR ALIGNMENT FOR WORST CASE NOISE
KEY CONTRIBUTIONS:
The assumption in HARMONY that worst case noise (WCN) is obtained through linear superposition is insufficient.
The simple linear Thevenin model of HARMONY is inaccurate for large values of noise, because transistor are no longer in triode region. Replaced by a slightly better PWL version.
HARMONY assumption that excludes contribution of aggressors whose noise peaks are not within timing window is inaccurate for large pulse widths.
This paper also contributes to improved worst case delay calculation through accurate worst case noise calculation.

22. Linearity and Victim Driver model
Capacitive coupling effects depend on the characteristics of drivers, interconnects and receivers. Interconnect coupling network consists of resistors and capacitors. The receiver functions as a loading capacitor.
Aggressor driver is usually modeled by its Thevenin equivalent circuit or Norton equivalent circuit
When the noise amplitude resulting from switching of all the acting aggressors is small, the quiet victim driver works in its linear region, so it can also be treated as a linear element.
However, with stronger coupling, noise is no longer small. Thus the assumption that the victim’s driver is in its linear range may not be true.

23. Aligning Aggressors for WCN

24. Alignment with Actual timing
Aggressor alignment generates sweep line.
Using sweep line and the actual timing windows of aggressors we can find out Worst Case Noise.

25. Aggressor alignment with timing constraints
Effective pulse width is a measure of range of noise waveform and is defined as :

26. Introduction
Motivation for Static Noise Analysis (SNA)
Noise Margin criteria
Harmony: SNA seed paper
Aggressor alignment for worst case noise
SNA using Timing Windows
Non-linear superposition of noise sources
Conclusions
References

27. STATIC NOISE ANALYSIS WITH TIMING WINDOWS
KEY CONTRIBUTIONS :
Timing of injected noise needs to be considered before flagging it as violation.
Timing of injected noise should be aligned with clock of register.
Timing window of the noise should be propagated down the path instead of just the DC value.
New algorithm that back annotates victim’s victim noise also.

28. NOISE PROPAGATION ANALOGY
Conceptually, noise glitches propagate through logic gates just as switching signals propagate through logic gates.
Static noise analysis calculates the early and late arrival times of noise in every net.
The early and late arrival times at register inputs are checked against the clock arrival time tCK and the setup and hold times to determine timing violation.

29. NOISE WINDOW COMPUTATION AND PROPAGATION

30. NOISE WINDOW COMPUTATION AND PROPAGATION – Contd.

31. Introduction
Motivation for Static Noise Analysis (SNA)
Noise Margin criteria
Harmony: SNA seed paper
Aggressor alignment for worst case noise
SNA using Timing Windows
Non-linear superposition of noise sources
Conclusions
References

32. ACCURATE NOISE ANALYSIS USING NON-LINEAR MODELING
Non-linearity of noise sums at the victim driver are serious considerations.
Consider the case where the victim driver is modeled as linear resistive element.
Compared with spice simulation the linear superposition model is very inaccurate.
This is because the victim drivers are no longer in a linear mode.

33. NOISE MACROMODEL
Victim driver is modeled as a Voltage Controlled Current Source (VCCS)
Input/Output voltage loading curves are obtained in a tabular form that is represented as:
The aggressor is modeled as the original thevenin voltage source as it doesn’t comprimise accuracy.

34. MULTIPLE GLITCH PROPAGATION
Simultaneous glitch propagation is possible using the combined loading characteristic defined as:
where
For multiple input glitches, the loading curve assumes a point with equal input noise glitch levels.

35. ACCURATE STATIC NOISE ANALYSIS
The total noise glitch at the Victim driver point, using Quasi Linear Transient Analysis is given by a Two pole model
Waveform-collapsing algorithm expresses the analytical triplet interms of noise glitch parameters like Amplitude VM, Area A,width and time-to-peak, with the initial relation.
Compute the roots of the following equation and get V(t):

36. Accurate Static Noise Analysis. Contd
Overall voltage at the victim receiving end can be computed by
Noise injected by coupling aggressors is onto victim receiving end is calculated using MOR techniques.
For noise propagating from victim driver, the following closed form expression is used

37. Results Final noise at the receiving end is now the sum:
Results show that QLTA method gives much closer results to that of spice simulation (ELDO)

38. CONCLUSIONS - SURVEY RECAP
The definition of and basic criteria for evaluating Static Noise will be discussed using [1].
The seed paper [2] is discussed in detail for its Macro level and Global level Static noise analysis methods.
The paper [3] describing Aggressor alignment technique for worst case crosstalk noise estimation was discussed and it has 3 major improvements over [2] the seed paper.
The next paper [4] which contributes new methods to accurately predict static noise injection using noise window propagation and register sensitive window computation was presented. This has added advantage to that of [3] because of noise window propagation.
Standard cell non-linear effects on noise glitch waveform that is described in [5]. This shows that existing papers [1] to [4] consider the linear superposition of noise which is inaccurate and improves on it.

39. Areas for potential improvements
Harmony – Resistance of interconnects not considered for Macro analysis
Non-linearity of superimposition.
Static noise analysis with windows – The delay for propagation of static noise is considered the same as digital signal propagation delay which is not true.
Simplified I_DC= f(Vin,Vout), assumes equal Vin for all noise glitches at inputs of gates. Better method is required.

40. REFERENCES
[1] Jan Lohstroh Evert Seevinck, Andjan De Groot “Worst-Case Static Noise Margin Criteria for Logic Circuits and Their Mathematical Equivalence”
[2] K. L. Shepard, V. Narayanan, P. C. Elmendorf, and G. Zheng, “Global Harmony: Coupled Noise Analysis for Full- Chip RC Interconnect Networks,” in Proc. Intl. Conf. on Computer-Aided Design, Nov. 1997, pp
[3] L. H. Chen, M. Marek-Sadowska, “Aggressor alignment for worst-case crosstalk noise,” IEEE Tran. Computer-Aided Design, vol. 20, no. 5, pp May 2001.
[3] Ken Tseng, Vinod Kariat “Static Noise Analysis with Noise Windows”
[4] Cristiano Forzan, Davide Pandini “A Complete Methodology for an Accurate Static Noise Analysis “Proceedings of the conference on Design, automation and test in Europe, p.812, March 04-08, 2002